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公开(公告)号：US20220352817A1
公开(公告)日：2022-11-03
申请号：US17866372
申请日：2022-07-15
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC: H02M3/07
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US20220345149A1
公开(公告)日：2022-10-27
申请号：US17723225
申请日：2022-04-18
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Abhishek JAIN , Sharad GUPTA
IPC: H03M3/00
Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.
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公开(公告)号：US20220334865A1
公开(公告)日：2022-10-20
申请号：US17657856
申请日：2022-04-04
Inventor： Roberto Colombo , Vivek Mohan Sharma
Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.
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公开(公告)号：US11476018B2
公开(公告)日：2022-10-18
申请号：US17385625
申请日：2021-07-26
Applicant: STMicroelectronics International N.V.
Inventor： Mohit Kaushik , Anil Kumar
Abstract: An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2X−1, each having a resistance equal to R*(2Y)*i, i being an index having a value ranging from 1 to 2X−1, a first of the M resistors having a resistance of R*2Y, a last of the M resistors having a resistance of R*2Y*(2X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.
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公开(公告)号：US20220321111A1
公开(公告)日：2022-10-06
申请号：US17673214
申请日：2022-02-16
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL
IPC: H03K5/02
Abstract: A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.
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Patent Agency Ranking
公开(公告)号：US11442108B1
公开(公告)日：2022-09-13
申请号：US17477237
申请日：2021-09-16
Applicant: STMicroelectronics International N.V.
IPC: G01R31/3185 , G01R31/317
Abstract: A circuit includes: a first power domain including: an isolation cell, a first selection circuit having inputs for receiving a first functional signal and a first test signal and an output for controlling the isolation cell, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation cell; a second power domain including: a first circuit having an input coupled to a signal output of the isolation cell, a first observation element coupled to the signal output of the isolation cell, and a second observation element coupled to an output of the first circuit; where, when in test mode, the first selection circuit controls the isolation cell based on the first test signal, and the second selection circuit provides the second test signal to the signal input of the isolation cell.
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公开(公告)号：US11418200B2
公开(公告)日：2022-08-16
申请号：US17507221
申请日：2021-10-21
Applicant: STMicroelectronics International N.V.
Inventor： Ankit Gupta , Sagnik Mukherjee
Abstract: A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.
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公开(公告)号：US20220238150A1
公开(公告)日：2022-07-28
申请号：US17721956
申请日：2022-04-15
Applicant: STMicroelectronics International N.V.
Inventor： Anuj GROVER , Tanmoy ROY
IPC: G11C11/408 , G11C5/02 , G11C11/4091 , G11C11/4096
Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.
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公开(公告)号：US11381207B2
公开(公告)日：2022-07-05
申请号：US16838315
申请日：2020-04-02
Applicant: STMicroelectronics International N.V.
Inventor： Riju Biswas
Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.
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公开(公告)号：US11380393B2
公开(公告)日：2022-07-05
申请号：US17129016
申请日：2020-12-21
Applicant: STMicroelectronics International N.V.
Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.
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