公开(公告)号：US20190385654A1

公开(公告)日：2019-12-19

申请号：US16551981

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C8/18 ,  G11C16/08 ,  G11C16/28 ,  G11C16/32

Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.

公开(公告)号：US20190371378A1

公开(公告)日：2019-12-05

申请号：US16167340

申请日：2018-10-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10 ,  H03K5/156

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20190311753A1

公开(公告)日：2019-10-10

申请号：US16452436

申请日：2019-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

公开(公告)号：US10437514B2

公开(公告)日：2019-10-08

申请号：US15722769

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US20190265913A1

公开(公告)日：2019-08-29

申请号：US16413475

申请日：2019-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing, an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US10395704B2

公开(公告)日：2019-08-27

申请号：US15853514

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C8/18 ,  G11C16/32 ,  G11C16/28 ,  G11C16/08

Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.

公开(公告)号：US10153030B2

公开(公告)日：2018-12-11

申请号：US15590972

申请日：2017-05-09

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C7/10

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US20180330775A1

公开(公告)日：2018-11-15

申请号：US15590972

申请日：2017-05-09

Applicant: Micron Technology, Inc.

Inventor： HYUN YOO LEE ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2207/2272

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US09881658B2

公开(公告)日：2018-01-30

申请号：US14505740

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Jacob Robert Anderson ,  Huy Vo

IPC: G11C7/20 ,  H01L25/065 ,  G11C29/00 ,  G11C29/32 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C7/20 ,  G11C29/003 ,  G11C29/32 ,  G11C29/50012 ,  G11C2029/0407 ,  H01L25/0657

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

公开(公告)号：US09236112B1

公开(公告)日：2016-01-12

申请号：US14485293

申请日：2014-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： George B. Raad ,  Kang-Yong Kim

IPC: G11C7/00 ,  G11C11/4094

CPC classification number: G11C11/4094 ,  G11C11/4076

Abstract: Methods and apparatuses are disclosed including an apparatus that includes a controller circuit configured to access a first subarray of a memory and to access a second subarray of the memory subsequent to accessing the first subarray but contemporaneous with precharging a portion of the first subarray by a precharge circuit associated with the first subarray.

Abstract translation: 公开了一种方法和装置，包括一种装置，其包括控制器电路，该控制器电路被配置为访问存储器的第一子阵列，并且在访问第一子阵列之后访问存储器的第二子阵列，但同时通过预充电对第一子阵列的一部分进行预充电 电路与第一个子阵列相关联。