公开(公告)号：US20190213137A1

公开(公告)日：2019-07-11

申请号：US16022714

申请日：2018-06-29

Applicant: Silicon Motion Inc.

Inventor： Chien-Cheng Lin ,  Chia-Chi Liang ,  Jie-Hao Lee

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises: reading a logical address to physical address (L2P) mapping table from the flash memory module; compressing the L2P mapping table to generate a compressed mapping table, wherein the compressed mapping table records a reference physical address and whether a corresponding physical address of each logical address is the reference physical address plus an offset value; and when receiving a read command asking for reading data corresponding to a specific logical address, referring to the compressed mapping table to determine a specific physical address corresponding to the specific logical address, and reading the data from the flash memory module according to the specific physical address.

公开(公告)号：US20190205497A1

公开(公告)日：2019-07-04

申请号：US16049803

申请日：2018-07-30

Applicant: Silicon Motion Inc.

Inventor： Shih-Hsiang Tai

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F3/0484 ,  G06F2217/06 ,  G06F2217/84

Abstract: The present invention provides a circuit design method, wherein the circuit design comprises the steps of: designing a plurality of paths, wherein each path comprises a plurality of elements; determining if the paths have enough timing margin to determine at least one specific path; and replacing at least one specific element within the specific path by a configurable gate array cell, wherein a function of the configurable gate array cell is the same as a function of the specific element.

公开(公告)号：US20190205248A1

公开(公告)日：2019-07-04

申请号：US16231589

申请日：2018-12-23

Applicant: Silicon Motion Inc.

Inventor： Chao-Kuei Hsieh

IPC: G06F12/02 ,  G06F3/08 ,  G06F3/06 ,  G11C16/26 ,  G11C16/16 ,  G11C7/10

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

公开(公告)号：US20190205047A1

公开(公告)日：2019-07-04

申请号：US16226820

申请日：2018-12-20

Applicant: SILICON MOTION INC.

Inventor： CHAO-KUEI HSIEH

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0679

Abstract: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

公开(公告)号：US10338843B2

公开(公告)日：2019-07-02

申请号：US15097785

申请日：2016-04-13

Applicant: Silicon Motion, Inc.

Inventor： Hsu-Ping Ou ,  Chih-Kang Kung

IPC: G06F12/10 ,  G06F3/06

Abstract: A method for moving data internally, performed by a processing unit, including at least the following steps. The processing unit transmits partial copyback read commands to a storage sub-unit through an access interface, where each partial copyback read command is used to direct logic circuits of the storage sub-unit to store partial data of a page of the storage sub-unit in a designated location of a data buffer of the storage sub-unit. The processing unit further transmits a copyback write command to the storage sub-unit through the storage sub-unit for programming the data of the data buffer in a new page of the storage sub-unit.

公开(公告)号：US20190196960A1

公开(公告)日：2019-06-27

申请号：US16229073

申请日：2018-12-21

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng LIN

IPC: G06F12/02 ,  G06F3/06

Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is shown. The non-volatile memory is programmed using one-shot programming, wherein N pages are programmed in one round of one-shot programming and N is a number greater than one. A control unit corrects the final page indicator of an active block of the non-volatile memory in a power recovery procedure to cope with a sudden power-off event, to point the final page indicator to a final page among N pages of one round of one-shot programming.

公开(公告)号：US20190188125A1

公开(公告)日：2019-06-20

申请号：US16039787

申请日：2018-07-19

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin

IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06 ,  G11C16/16 ,  G06F13/24

Abstract: A data storage device includes a memory device, an SRAM and a controller. The memory device includes a first buffer configured to store data of a plurality of consecutive logical pages. The SRAM stores a first mapping table. The first mapping table records which logical page the data stored in each physical page of the first buffer directs to. The controller is coupled to the memory device and the SRAM. When the controller performs an erase operation to erase the data stored in the first buffer in response to an erase command, the controller checks whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished. The predetermined number (M) is a positive integer greater than 1.

公开(公告)号：US20190165817A1

公开(公告)日：2019-05-30

申请号：US16038147

申请日：2018-07-17

Applicant: Silicon Motion Inc.

Inventor： Shiuan-Hao Kuo

IPC: H03M13/29 ,  G06F11/10

Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

公开(公告)号：US10304557B2

公开(公告)日：2019-05-28

申请号：US15606164

申请日：2017-05-26

Applicant: Silicon Motion, Inc.

Inventor： Wen-Chun Jian

IPC: G06F3/06 ,  G11C29/48 ,  G11C16/20

Abstract: A data storage device includes a flash memory and a controller. The controller is coupled to the flash memory and includes a ROM which stores a boot code. In an initialization procedure of the data storage device, the controller does not access the flash memory and receives a debug code from an external device, and executes the boot code and the debug code to complete the initialization procedure.

公开(公告)号：US20190155531A1

公开(公告)日：2019-05-23

申请号：US16260142

申请日：2019-01-29

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.