公开(公告)号：US12192531B2

公开(公告)日：2025-01-07

申请号：US18479663

申请日：2023-10-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Han Boon Teo ,  Chong Soon Lim ,  Hai Wei Sun ,  Che-Wei Kuo ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/107 ,  H04N19/176 ,  H04N19/186

Abstract: A decoder includes memory and a processor coupled to the memory and configured to: generate a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component; clip the first coefficient value such that the clipped first coefficient value is within a first range from −27 to 27−1; generate a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component; clip the second coefficient value such that the clipped second coefficient value is within a second range different from the first range; generate a third coefficient value by adding the clipped first coefficient value to the clipped second coefficient value; and generate a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US12184887B2

公开(公告)日：2024-12-31

申请号：US18473027

申请日：2023-09-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Sughosh Pavan Shashidhar ,  Ru Ling Liao ,  Hai Wei Sun ,  Han Boon Teo ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi

IPC: H04N19/00 ,  H04N19/119 ,  H04N19/176 ,  H04N19/513 ,  H04N19/96

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry corrects a base motion vector using a correction value in a fixed direction; and encodes a current partition by using the corrected base motion vector corrected. The correction value is specified by an index indicating one of correction values included in a table. The table is selected from among a plurality of tables, wherein the correction values in one of the plurality of tables have different increments from the correction values in another one of the plurality of tables.

公开(公告)号：US12160614B2

公开(公告)日：2024-12-03

申请号：US17750950

申请日：2022-05-23

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes a video using (i) a decoding parameter set (DPS) which is identified based on presence of the DPS in a bitstream and (ii) a sequence parameter set (SPS) which is identified based on an identifier for the SPS.

公开(公告)号：US12143584B2

公开(公告)日：2024-11-12

申请号：US17508289

申请日：2021-10-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/12 ,  H04N19/14 ,  H04N19/147 ,  H04N19/176 ,  H04N19/46 ,  H04N19/61 ,  H04N19/65 ,  H04N19/119

Abstract: A decoder comprising a processor and a memory, wherein the processor, using the memory, inverse quantizes data corresponding to a current block of an image performs an inverse secondary transform, using one candidate of the inverse secondary transform selected from candidates of the inverse secondary transform, on a result of the inverse quantization to generate second transform coefficients, the candidates of the inverse secondary transform including transform bases for the inverse secondary transform and a skip of the inverse secondary transform and performs an inverse primary transform, using one candidate of the inverse primary transform selected from candidates of the inverse primary transform, on the second transform coefficients or the result of the inverse quantization to generate first transform coefficients, the candidates of the inverse primary transform including transform bases for the inverse primary transform.

公开(公告)号：US12132886B2

公开(公告)日：2024-10-29

申请号：US17844936

申请日：2022-06-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/105 ,  H04N19/15

CPC classification number: H04N19/105 ,  H04N19/15

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry switches between storing and not storing of a decoded picture buffer (DPB) parameter related to a DPB in a common header shared between layers in layer groups each including at least one output layer, according to whether or not all the layer groups in a bitstream each include only one layer.

公开(公告)号：US12120349B2

公开(公告)日：2024-10-15

申请号：US17889580

申请日：2022-08-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi ,  Masato Ohkawa ,  Hideo Saitou

IPC: H04N11/02 ,  H04N19/124 ,  H04N19/176 ,  H04N19/44 ,  H04N19/60

CPC classification number: H04N19/60 ,  H04N19/124 ,  H04N19/176 ,  H04N19/45

Abstract: An encoder which transforms a current block to be encoded in an image to encode the current block includes circuitry and memory. The circuitry, using the memory: determines a plurality of first transform basis candidates and transforms the current block using a transform basis included in the plurality of first transform basis candidates determined, when the current block has a first size; and determines one or more second transform basis candidates different from the plurality of first transform basis candidates and transforms the current block using a transform basis included in the one or more second transform basis candidates determined, when the current block has a second size larger than the first size.

公开(公告)号：US12108092B2

公开(公告)日：2024-10-01

申请号：US18226930

申请日：2023-07-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Noritaka Iguchi ,  Tadamasa Toma

IPC: H04N21/231 ,  H04H60/40 ,  H04J3/06 ,  H04L65/611 ,  H04N21/234 ,  H04N21/235 ,  H04N21/2365 ,  H04N21/43 ,  H04N21/434 ,  H04N21/63 ,  H04N21/845

CPC classification number: H04N21/231 ,  H04H60/40 ,  H04J3/0661 ,  H04L65/611 ,  H04N21/234 ,  H04N21/235 ,  H04N21/2365 ,  H04N21/43072 ,  H04N21/4347 ,  H04N21/631 ,  H04N21/8456

Abstract: A transmitting method stores data making up a coded stream into a predetermined data unit and transmits the stored data in the predetermined data unit. The transmitting method further generates presentation time information indicating a presentation time of the predetermined data unit, based on reference time information received from an external source; and transmits the predetermined data unit, first control information which includes the generated presentation time information, and second control information which includes leap second information indicating whether or not the presentation time information is a time that is before a leap second adjustment. A receiving method receives the predetermined data unit, first control information, and second control information; and reproduces the received predetermined data unit based on the first and second control information that are received.

公开(公告)号：US20240323401A1

公开(公告)日：2024-09-26

申请号：US18734115

申请日：2024-06-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

CPC classification number: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.

公开(公告)号：US12081752B2

公开(公告)日：2024-09-03

申请号：US17728286

申请日：2022-04-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.

公开(公告)号：US12075070B2

公开(公告)日：2024-08-27

申请号：US17681105

申请日：2022-02-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/30 ,  H04N19/103 ,  H04N19/157 ,  H04N19/169 ,  H04N19/70

CPC classification number: H04N19/30 ,  H04N19/103 ,  H04N19/157 ,  H04N19/188 ,  H04N19/70

Abstract: An encoder includes: memory; and circuitry coupled to the memory and configured to generate an encoded bitstream. In the encoder, when a multi-layer structure is to be included in the encoded bitstream to be generated, the circuitry generates the encoded bitstream by including in the encoded bitstream (i) a sequence parameter set that refers to a video parameter set and (ii) a network abstraction layer (NAL) unit having a layer identification (ID) greater than zero in the multi-layer structure, and when the multi-layer structure is not to be included in the encoded bitstream to be generated, the circuitry generates the encoded bitstream by including in the encoded bitstream a sequence parameter set that does not refer to the video parameter set.