公开(公告)号：US07423567B2

公开(公告)日：2008-09-09

申请号：US11531144

申请日：2006-09-12

Applicant: John L. Melanson

Inventor： John L. Melanson

IPC: H03M3/00 ,  H03M1/12

CPC classification number: H03M3/412 ,  H03M3/424 ,  H03M3/452 ,  H03M3/454

Abstract: An analog-to-digital converter (ADC) having a reduced number of quantizer output levels provides for reduced complexity and power consumption along with improved linearity. The analog-to-digital converter includes a loop filter, a quantizer for quantizing the output of the loop filter and a digital integrator for integrating the output of the quantizer. A difference circuit is included in the converter that produces a signal proportional to the difference between the present value and a previous value of the digital integrator output and provides feedback to the loop filter. The number of levels of the quantizer output is thereby reduced with respect to the modulator output, since the quantizer is operating on a feedback signal that represents changes in the output of the converter modulator rather than the modulator output itself.

Abstract translation: 具有减少的量化器输出电平数量的模数转换器（ADC）提供降低的复杂性和功耗以及改进的线性度。 模数转换器包括环路滤波器，用于量化环路滤波器的输出的量化器和用于对量化器的输出进行积分的数字积分器。 差分电路包括在转换器中，产生与当前值和数字积分器输出的先前值之间的差成比例的信号，并向环路滤波器提供反馈。 量化器输出的电平数量因此相对于调制器输出而减少，因为量化器在表示转换器调制器的输出的变化而不是调制器输出本身的反馈信号上操作。

公开(公告)号：US07391842B1

公开(公告)日：2008-06-24

申请号：US11432113

申请日：2006-05-11

Applicant: John Laurence Melanson

Inventor： John Laurence Melanson

IPC: H03D3/24

CPC classification number: H03L7/185 ,  G06F1/0321 ,  G06F1/0353 ,  H03L2207/12

Abstract: Clock signal generation circuitry includes input circuitry for receiving a frequency control input signal and a clock signal and generating a memory address therefrom, a memory for storing digital data indexed by the memory address and representing real and imaginary parts of a complex digital waveform, and digital to analog conversion circuitry. The digital to analog conversion circuitry includes real-part digital to analog conversion circuitry for converting digital data retrieved from the memory and representing the real part of the complex waveform into a real-part analog signal and imaginary-part digital to analog conversion circuitry for converting digital data retrieved from the memory and representing the imaginary part of the complex waveform into an imaginary-part analog signal. The clock signal generation circuitry also includes analog filtering circuitry having real-part filtering circuitry for filtering the real-part analog signal to generate a filtered real-part analog signal and imaginary-part filtering circuitry for filtering the imaginary-part analog signal to generate a filtered imaginary-part analog signal. Analog to digital conversion circuitry is provided for converting the filtered real-part and imaginary-part analog signals into a digital clock signal at a rate near an integer multiple of a frequency of the filtered real-part and imaginary-part analog signals.

Abstract translation: 时钟信号产生电路包括用于接收频率控制输入信号和时钟信号并从其产生存储器地址的输入电路，用于存储由存储器地址索引并表示复数数字波形的实部和虚部的数字数据的存储器，以及数字 到模拟转换电路。 数模转换电路包括实部数字到模拟转换电路，用于转换从存储器检索的数字数据，并将复数波形的实部表示为实部模拟信号和虚部数模转换电路，用于转换 从存储器检索的数字数据，并将复数波形的虚部表示成虚部模拟信号。 时钟信号产生电路还包括具有实部滤波电路的模拟滤波电路，用于对实部模拟信号进行滤波以产生经滤波的实部模拟信号和虚部滤波电路，用于对虚部模拟信号进行滤波以产生 滤波的虚部模拟信号。 提供模数转换电路，用于将滤波的实部和虚部模拟信号以接近滤波后的实部和虚部模拟信号的频率的整数倍的速率转换为数字时钟信号。

公开(公告)号：US20080144534A1

公开(公告)日：2008-06-19

申请号：US11611120

申请日：2006-12-14

Applicant: Kevin P. Gross

Inventor： Kevin P. Gross

IPC: H04L12/28

CPC classification number: H04L43/045 ,  H04L43/0852

Abstract: A method is provided for determining the length of node-to-node links in a computer network. The method includes measuring the forwarding time for each node-to-node link in the network, eliminating queuing time from each forwarding time measurement, determining and subtracting store-forward time from each forwarding time measurement, determining and subtracting execution time from each forwarding time measurement to obtain a propagation time for a signal being transmitted on each node-to-node link and, based upon the propagation time for each node-to-node link, calculating a length of each node-to-node link. A network map may also be derived by identifying internal nodes in the network, translating each store-forward time into a hop count, constructing a connectivity map of the network including a connection map of internal nodes and superimposing the calculated link lengths onto the connectivity map to determine cable length between any internal nodes with more than two connections.

Abstract translation: 提供了一种用于确定计算机网络中的节点到节点链路的长度的方法。 该方法包括测量网络中每个节点到节点链路的转发时间，消除每个转发时间测量的排队时间，从每个转发时间测量确定和减去存储前进时间，从每个转发时间确定和减去执行时间 测量以获得在每个节点到节点链路上传输的信号的传播时间，并且基于每个节点到节点链路的传播时间来计算每个节点到节点链路的长度。 还可以通过识别网络中的内部节点，将每个存储转发时间转换成跳数来构建网络映射，构建包括内部节点的连接映射的网络的连通性映射，并将所计算的链路长度叠加到连接图上 以确定具有多于两个连接的任何内部节点之间的电缆长度。

公开(公告)号：US07345514B2

公开(公告)日：2008-03-18

申请号：US11361209

申请日：2006-02-24

Applicant: Bruce Duewer

Inventor： Bruce Duewer

IPC: H03L7/00

CPC classification number: H03M1/00 ,  H03K17/22 ,  H03M3/30

Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is an internal reference voltage pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset and wherein the internal reference voltage pin is normally used by the integrated circuit for internally generating a reference voltage.

Abstract translation: 集成电路具有耦合到电路的电路和引脚。 其中一个引脚是内部参考电压引脚，其引脚信号被设置在引脚信号的正常范围之外的水平，使得集成电路被指示复位，并且其中内部参考电压引脚通常由 内部产生参考电压的集成电路。

公开(公告)号：US07307565B1

公开(公告)日：2007-12-11

申请号：US11315549

申请日：2005-12-22

Applicant: John L. Melanson

Inventor： John L. Melanson

IPC: H03M3/00

CPC classification number: H03M7/3006

Abstract: A signal processing system matches, within a band of near out-of-band frequencies, the frequency response trends of a delta sigma modulator noise transfer function (NTF) and frequency response trends of a low pass finite impulse response (FIR) filter to provide noise attenuation in in-band frequencies and near out-of-band frequencies. More specifically, in at least one embodiment, the signal processing system matches, within the band of near out-of-band frequencies, a gradient trending toward increasing energy as the near out-of-band frequencies increase of the NTF with a gradient trending toward increasing attenuation by a FIR filter to improve attenuation of near out-of-band energy in an output signal of the signal processing system. Operation of the delta sigma modulator generates near out-of-band noise. Improving attenuation of the near out-of-band energy helps prevent the near out-of-band energy from being modulated into in-band frequencies, i.e. frequencies of a signal of interest.

Abstract translation: 信号处理系统在接近带外频率的频带内匹配ΔΣ调制器噪声传递函数（NTF）的频率响应趋势和低通有限脉冲响应（FIR）滤波器的频率响应趋势，以提供 带内频率和近带外频率的噪声衰减。 更具体地，在至少一个实施例中，信号处理系统在接近带外频率的频带内匹配趋向于增加的能量的梯度，因为具有渐变趋势的NTF的接近带外频率增加 通过FIR滤波器增加衰减，以改善信号处理系统的输出信号中的近带外能量的衰减。 ΔΣ调制器的操作产生近于带外的噪声。 改善近带外能量的衰减有助于防止近端带外能量被调制到带内频率，即感兴趣信号的频率。

公开(公告)号：US07280550B1

公开(公告)日：2007-10-09

申请号：US10323016

申请日：2002-12-18

Applicant: Gerrit Eimbertus Rosenboom

Inventor： Gerrit Eimbertus Rosenboom

IPC: H04L12/28 ,  H04J3/06

CPC classification number: H04L12/42 ,  H04J3/0682 ,  H04L7/0008

Abstract: In a ring topology digital network propagation delay is reduced A master node transmits a clock signal into the network in one direction. Each slave node propagates the signal to the next slave node without regeneration until the signal is received by the master node. The amount of time the signal takes to travel around the ring, is measured and is the total ring propagation delay. The master node then transmits a clock signal in both directions to the first slave node which measures the difference in their arrival times and transmits the difference to the master node. The process is repeated for each other slave node. Based upon each difference the master node computes the propagation delay for each ring segment. The master node transmits to each slave node the corresponding ring segment propagation delay and each slave node adjusts the phase of the node's clock.

Abstract translation: 在环形拓扑中，数字网络传播延迟降低主节点在一个方向上将时钟信号发送到网络。 每个从节点将信号传播到下一个从节点而不进行再生，直到信号被主节点接收。 测量信号在环周围行进的时间量，并且是总环形传播延迟。 主节点然后将两个方向的时钟信号发送到测量其到达时间差的第一从节点，并将该差发送到主节点。 对于每个其他从节点重复该过程。 基于每个差异，主节点计算每个环段的传播延迟。 主节点向每个从节点发送相应的环路段传播延迟，每个从节点调整节点时钟的相位。

公开(公告)号：US07277035B1

公开(公告)日：2007-10-02

申请号：US11428108

申请日：2006-06-30

Applicant: Zhong You ,  Brian David Trotter ,  John L. Melanson

Inventor： Zhong You ,  Brian David Trotter ,  John L. Melanson

IPC: H03M1/66

CPC classification number: H03M3/34 ,  H03M3/504

Abstract: A method and apparatus for reducing noise in a digital-to-analog converter (DAC) having a chopper amplifier output stage provides improved DAC performance. A switched-current output provided from a digital filter is coupled to the input of a chopper amplifier. The current switches are non-uniform, so that extra zeros are provided at the chopping frequency of the chopping amplifier, thereby reducing noise that would otherwise be aliased in-band at the output of the chopper amplifier. The current switches may include a first set of half-magnitude switches followed by a set of full-magnitude switches and finally by another set of half-magnitude switches having a size equal to that of the first set.

Abstract translation: 用于降低具有斩波放大器输出级的数模转换器（DAC）中的噪声的方法和装置提供改进的DAC性能。 从数字滤波器提供的开关电流输出耦合到斩波放大器的输入端。 电流开关是不均匀的，因此在斩波放大器的斩波频率处提供额外的零，从而减少否则将在斩波放大器的输出处带内的混叠噪声。 电流开关可以包括第一组半幅度开关，随后是一组全幅度开关，最后还包括具有等于第一组尺寸的另一组半幅度开关。

公开(公告)号：US07262717B2

公开(公告)日：2007-08-28

申请号：US11387093

申请日：2006-03-22

Applicant: John L. Melanson ,  Stephen Alan Turk

Inventor： John L. Melanson ,  Stephen Alan Turk

IPC: H03M7/00

CPC classification number: H03H17/0416 ,  H03H17/0444

Abstract: Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. Input data samples provided at a first sample rate are converted to output data samples at a second sample rate unequal to the first sample rate. An Infinite Impulse Response filter having internal states are updated at the first sample rate filters the input data samples in, to produce filtered data samples at the first sample rate. Output data samples are output at the second sample rate, where each output data sample is created as the sum of at least two intermediate products, a first intermediate product and a second intermediate product. The first intermediate product is defined by a first function of the internal states multiplied by a first function of the time difference between output samples and internal state updates, and the second intermediate product is defined by a second function of the internal states multiplied by a second function of the time difference between output samples and internal state updates.

公开(公告)号：US07262654B2

公开(公告)日：2007-08-28

申请号：US11036082

申请日：2005-01-14

Applicant: Murari Kejariwal ,  Gowtham Vemulapalli ,  John Laurance Melanson

Inventor： Murari Kejariwal ,  Gowtham Vemulapalli ,  John Laurance Melanson

IPC: H03F1/02

CPC classification number: H03F3/387 ,  H03F2200/261

Abstract: An operational amplifier including at least one amplifier stage and chopping circuitry for chopping an input signal to the amplifier stage and an output signal from the chopping signal having a frequency randomly varying within the selected frequency band.

Abstract translation: 一种运算放大器，包括至少一个放大器级和用于将输入信号斩波到放大器级的斩波电路以及来自具有在所选频带内随机变化的频率的斩波信号的输出信号。

公开(公告)号：US07251231B2

公开(公告)日：2007-07-31

申请号：US10371824

申请日：2003-02-21

Applicant: Rajugopal Gubbi

Inventor： Rajugopal Gubbi

IPC: H04J3/00

CPC classification number: H04W28/16 ,  H04L12/2803 ,  H04L12/2816 ,  H04L12/403 ,  H04L29/06 ,  H04L29/06027 ,  H04L67/42 ,  H04L2012/2841 ,  H04L2012/2849 ,  H04N21/43615 ,  H04N21/43637 ,  H04W84/02

Abstract: A communication channel is controlled so as to dynamically accommodate network client requests for access thereto. The communication channel may be supported on a wireless link, such as a spread spectrum wireless link, and client requests for access thereto may be dynamically accommodated by allocating time slots for client transmissions on the wireless link. Providing a quiet time slot within which clients may request access to the communication channel may accommodate various client requests for access to the communication channel. These quiet slots may exist with other forward and reverse time slots which are superimposed on the communication channel, each forward and reverse time slot including one or more data frames. The forward and reverse time slots are preferably fixed, but negotiable, time periods. Each of the data frames may include a plurality of data packets, each of the data packets being variable in length. Preferably, each of the data packets includes error correction coding information as well as information which may be used to synchronize pseudo-random number generators of a transmitter and a receiver operating according to the communication protocol. Each of the data frames may further include link identification information that uniquely identifies a wireless link supporting the communication protocol.

Abstract translation: 控制通信信道以动态地适应网络客户端对其访问的请求。 可以在诸如扩频无线链路的无线链路上支持通信信道，并且可以通过为无线链路上的客户端传输分配时隙来动态地容纳对其的访问请求。 提供客户端可以请求访问通信信道的安静时隙可以适应用于访问通信信道的各种客户端请求。 这些安静时隙可以存在于其上叠加在通信信道上的其它正向和反向时隙，每个前向和反向时隙包括一个或多个数据帧。 正向和反向时隙优选地是固定的，但可协商的时间段。 每个数据帧可以包括多个数据分组，每个数据分组的长度是可变的。 优选地，每个数据分组包括纠错编码信息以及可以用于同步根据通信协议操作的发射机和接收机的伪随机数发生器的信息。 每个数据帧还可以包括唯一地标识支持通信协议的无线链路的链路标识信息。