摘要:
A switching converter controller and method for controlling a switch-mode converter in a hybrid discontinuous conduction mode (DCM)/continuous conduction mode (CCM) mode are disclosed. The hybrid mode involves using double (two) or more switching pulses in a switching period of a control signal for controlling the switch-mode converter. The switching period is defined by a switch on-time duration, a switch off-time duration, and an N number of switching pulses. N is an integer greater than one. An inductor current through the inductor of the switch-mode converter is zero before an initial switching pulse, is zero after a last switching pulse, and is non-zero for all other times within the switching period. The switch-mode-converter controller can be used as a power factor correction controller for a power factor corrector. The switch-mode converter controller can be implemented on a single integrated circuit.
摘要:
A switching converter controller and method for controlling a switch-mode converter in a hybrid discontinuous conduction mode (DCM)/continuous conduction mode (CCM) mode are disclosed. The hybrid mode involves using double (two) or more switching pulses in a switching period of a control signal for controlling the switch-mode converter. The switching period is defined by a switch on-time duration, a switch off-time duration, and an N number of switching pulses. N is an integer greater than one. An inductor current through the inductor of the switch-mode converter is zero before an initial switching pulse, is zero after a last switching pulse, and is non-zero for all other times within the switching period. The switch-mode converter controller can be used as a power factor correction controller for a power factor corrector. The switch-mode converter controller can be implemented on a single integrated circuit.
摘要:
An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要:
A switch-mode converter controller and method utilizes a comparator for receiving and comparing a sensed current and a peak current that is determined by a product of a multiplying factor, that is greater than or equal to two, and a target current. A finite state machine (FSM) is configured to operate the switch-mode converter in a discontinuous conduction mode (DCM). Responsive to the comparator, the FSM turns on the switch and observes an on-time duration of the switch until the sensed current reaches the peak current; calculates a switching period responsive to the peak current and the observed on-time duration; and varies the switching period responsive to the on-time duration and the multiplying factor such that an average of the sensed current equals the target current. The FSM can also be configured to alternatively operate the switch-mode converter in a continuous conduction mode (CCM).
摘要:
A pulse width modulation circuit for driving a full-bridge output load includes a pulse width modulation stage for generating, from an input data stream, a pulse width modulated data stream for driving a terminal of a full-bridge output load and another pulse width modulated data stream for driving another terminal of the full bridge output load. A delay circuit delays the another pulse width modulated data stream relative to the pulse width modulated data stream such that edges of the another pulse width modulated data stream and edges of the pulse width modulated data stream are temporally spaced.
摘要:
A data converter including a digital volume control for continuously scaling a received stream of digital audio data by a selected factor and a low noise delta-sigma modulator for re-quantizing a scaled digital data stream output from the digital volume control.
摘要:
A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal and measure a frequency ratio between a data clock frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing an explicit formula. In a further embodiment, the mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing a lookup table. In an additional embodiment, the mapping system tests an available set of operating modes, independent of any previous tests, to determine a suitable operating mode for the data converter.
摘要:
A system for determining a data converter operating mode including measurement circuitry operable to measure a master clock frequency by comparing a frequency of a master clock signal and a frequency of a fixed frequency clock signal and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In one particular embodiment, the fixed frequency clock signal is provided by an oscillator. In a further embodiment, the master clock signal is generated by multiplying the frequency of another clock signal.
摘要:
A switched capacitor circuit 300, including a sampling capacitor 303, switches 301, 304 for charging the sampling capacitor 303 during a charging phase, and switches 302, 305 for transferring charge from the sampling capacitor 303 to a load 313 in the feedback loop of an operational amplifier 312 during a dump phase. Circuitry 701 controls the discharge of sampling capacitor 303 during the dump phase to minimize transients at the input of the operational amplifier 312 and thereby minimize input threshold voltage variation.
摘要:
A delta-sigma modulator 400 includes circuitry 407 for selectively varying an order of the modulator to vary a modulation index of the delta sigma modulator.