公开(公告)号：US10331598B2

公开(公告)日：2019-06-25

申请号：US15896092

申请日：2018-02-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Itkin

IPC: G06F13/14 ,  H04J1/10 ,  G06F13/38 ,  G06F13/42 ,  H04L29/08

Abstract: A host computer connects to a data network via a host interface to a network interface controller A sideband interface connects the network interface controller to a baseboard management controller having a management network port for connection to a management network. A path is established in the network interface controller between the host interface the basement management controller via the sideband interface of the network interface controller to conduct data selectively between the management network and either the host central processing unit and the or internally in the network interface controller.

公开(公告)号：US20190171783A1

公开(公告)日：2019-06-06

申请号：US15829216

申请日：2017-12-01

Applicant: Mellanox Technologies Ltd.

Inventor： Alexander Martfeld

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F17/5063 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/66

Abstract: Methods and systems for designing an integrated circuit device are described. The method includes receiving RTL descriptions of the whole device and generating lower level component descriptions. The method further includes grouping the component descriptions into blocks, analyzing the component descriptions, and identifying block internal removable components based on the analysis. The method further includes removing the removable components. Reduced design is converted into gate-level descriptions. Finally, the method includes executing high quality and high efficiency device TOP level physical implementation and generation of physical and timing constrains for block level design.

公开(公告)号：US20190171612A1

公开(公告)日：2019-06-06

申请号：US16224834

申请日：2018-12-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Ariel Shahar ,  Roee Moyal ,  Ali Ayoub ,  Michael Kegan

IPC: G06F15/173 ,  G06F15/167 ,  G06F13/28 ,  H04L9/32 ,  H04L9/06

Abstract: A network adapter includes a network interface that communicates packets over a network, a host interface connected locally to a host processor and to a host memory, and processing circuitry, coupled between the network interface and the host interface, and is configured to receive in a common queue, via the host interface, (i) a processing work item specifying a source buffer in the host memory, a data processing operation, and a first address in the host memory, and (ii) an RDMA write work item specifying the first address, and a second address in a remote memory. In response to the processing work item, the processing circuitry reads data from the source buffer, applies the data processing operation, and stores the processed data in the first address. In response to the RDMA write work item the processing circuitry transmits the processed data, over the network, for storage in the second address.

公开(公告)号：US10303647B2

公开(公告)日：2019-05-28

申请号：US15202590

申请日：2016-07-06

Applicant: Mellanox Technologies Ltd.

Inventor： Adi Menachem ,  Shachar Raindel

IPC: G06F15/173 ,  G06F13/40 ,  G06F9/455 ,  G06F13/42

Abstract: Computing apparatus includes a central processing unit (CPU), which is configured to run concurrently multiple virtual machines, including at least first and second virtual machines. A peripheral component bus is connected to communicate with the CPU. Multiple peripheral devices are connected to communicate via the bus with the CPU and with others of the peripheral devices, including at least first and second peripheral devices that are each respectively partitioned into at least first and second functional entities, which are respectively assigned to serve the at least first and second virtual machines. Access control logic is configured to forward peer-to-peer communications initiated by the functional entities between the peripheral devices over the bus while inhibiting access in the peer-to-peer communications between the functional entities that are assigned to different ones of the virtual machines.

公开(公告)号：US10303635B2

公开(公告)日：2019-05-28

申请号：US15701461

申请日：2017-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuval Itkin

IPC: G06F13/38 ,  H04L29/06 ,  G06F11/20

Abstract: A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with a communication network. The multiple bus interfaces are configured to communicate with multiple respective Central Processing Units (CPUs) that support a management protocol and belong to a multi-CPU device, and with a Baseboard Management Controller (BMC). The processor is configured to, in response to a request to enumerate the bus interfaces that support the management protocol, report support of the management protocol over only a single bus interface, selected from among the multiple bus interfaces connecting the network adapter to the multi-CPU device, and exchange management packets over the communication network between the BMC and a remote management computer, wherein the management packets manage the entire multi-CPU device but traverse only the single selected bus interface.

公开(公告)号：US20190095776A1

公开(公告)日：2019-03-28

申请号：US15716761

申请日：2017-09-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Boaz Kfir ,  Noam Eilon ,  Meital Tsechanski ,  Itsik Levi

IPC: G06N3/04 ,  G06F9/30

Abstract: Computational apparatus includes an input buffer configured to hold a first array of input data and an output buffer configured to hold a second array of output data computed by the apparatus. A plurality of processing elements are each configured to compute a convolution of a respective kernel with a set of the input data that are contained within a respective window and to write a result of the convolution to a corresponding location in a respective plane of the output data. One or more data fetch units each read one or more segments of the input data from the input buffer. A shift register delivers the segments of the input data in succession to each of the processing elements in an order selected so that the respective window of each processing element slides in turn over a sequence of window positions covering the first array.

公开(公告)号：US20190095222A1

公开(公告)日：2019-03-28

申请号：US15717969

申请日：2017-09-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuval Itkin ,  Liran Liss

IPC: G06F9/44 ,  G06F13/40 ,  G06F13/42

Abstract: A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with a communication network. The multiple bus interfaces are configured to communicate with multiple respective Central Processing Units (CPUs) that belong to a multi-CPU device. The processor is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, and, in response to a request from the multi-CPU device to report the support of the Option-ROM functionality, to report the support of the Option-ROM functionality over only a single bus interface, selected from among the multiple bus interfaces connecting the network adapter to the multi-CPU device.

公开(公告)号：US20190074040A1

公开(公告)日：2019-03-07

申请号：US16121672

申请日：2018-09-05

Applicant: Mellanox Technologies, Ltd. ,  Bar-Ilan University

Inventor： Elad Mentovich ,  Narkis Geuli ,  Robert Giterman ,  Alexander Fish ,  Adam Teman

IPC: G11C7/10 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412

Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.

公开(公告)号：US20190034381A1

公开(公告)日：2019-01-31

申请号：US15659876

申请日：2017-07-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Diego Crupnicoff

IPC: G06F15/167 ,  G06F15/173 ,  H04L29/06

CPC classification number: G06F15/167 ,  G06F15/17331 ,  H04L67/1097 ,  H04L67/42

Abstract: Communication apparatus includes a host interface, configured to be coupled to a host processor having a host memory, and a network interface, which is configured to receive over a network from a sending node data packets conveying operations for execution in a sequential order on a predefined queue pair (QP), including at least a first packet conveying a posted write operation and a second packet conveying a non-posted write operation. Packet processing circuitry is configured to execute the posted write operation in accordance with the sequential order so as to write first data to the host memory prior to the execution of any subsequent operations in the sequential order, and to execute the non-posted write operation so as to write second data to the host memory while allowing one or more of the subsequent operations in the sequential order to be executed prior to completion of writing the second data.

公开(公告)号：US20190018192A1

公开(公告)日：2019-01-17

申请号：US16031428

申请日：2018-07-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Yaakov Gridish ,  Eran Aharon ,  Elad Mentovich ,  Sylvie Rockman

IPC: G02B6/14 ,  G02B6/028 ,  G02B6/26

CPC classification number: G02B6/14 ,  G02B6/0288 ,  G02B6/124 ,  G02B6/136 ,  G02B6/262 ,  G02B6/2852 ,  G02B2006/12095 ,  G02B2006/12147

Abstract: A waveguide having a gradient-index (GRIN) waveguide lateral coupler is provided. In an example embodiment, the waveguide comprises an active region. The refractive index profile of the active region is non-constant.