公开(公告)号：US20190074040A1

公开(公告)日：2019-03-07

申请号：US16121672

申请日：2018-09-05

申请人： Mellanox Technologies, Ltd. ,  Bar-Ilan University

发明人： Elad Mentovich ,  Narkis Geuli ,  Robert Giterman ,  Alexander Fish ,  Adam Teman

IPC分类号： G11C7/10 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412

摘要： A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.

公开(公告)号：US11127455B2

公开(公告)日：2021-09-21

申请号：US16699003

申请日：2019-11-28

申请人： Bar-Ilan University

发明人： Adam Teman ,  Amir Shalom ,  Robert Giterman ,  Alexander Fish

IPC分类号： G11C11/4096 ,  H01L27/108 ,  H01L23/528 ,  H01L27/02 ,  H01L29/78

摘要： A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

公开(公告)号：US11586778B2

公开(公告)日：2023-02-21

申请号：US16769664

申请日：2018-12-06

申请人： Bar-Ilan University

发明人： Robert Giterman ,  Itamar Levi ,  Yoav Weizman ,  Osnat Keren ,  Alexander Fish ,  Maoz Vizentovski

IPC分类号： G06F21/75 ,  G06F13/16 ,  G06F21/72 ,  G11C7/24

摘要： A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.

公开(公告)号：US11309008B2

公开(公告)日：2022-04-19

申请号：US17257893

申请日：2019-07-09

申请人： Bar-Ilan University

发明人： Robert Giterman ,  Adam Teman

IPC分类号： G11C11/34 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096

摘要： An FD-SOI GC-edRAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal put connected to a RWL, for inputting a read trigger signal; at least one body voltage terminal connected to a respective body voltage; and multiple FD-SOI transistors. The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.

公开(公告)号：US10002660B2

公开(公告)日：2018-06-19

申请号：US15632555

申请日：2017-06-26

申请人： Bar-Ilan University

发明人： Robert Giterman ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

IPC分类号： G11C5/06 ,  G11C11/41 ,  G11C11/403 ,  G11C11/4097 ,  G11C5/02 ,  G11C7/10 ,  H01L27/11 ,  G11C8/14 ,  G11C8/16 ,  G11C11/405

CPC分类号： G11C11/41 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/1104

摘要： A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

公开(公告)号：US09691445B2

公开(公告)日：2017-06-27

申请号：US15306796

申请日：2015-04-30

申请人： Bar-Ilan University

发明人： Robert Giterman ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

IPC分类号： G11C5/06 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/412 ,  G11C5/02 ,  H01L27/11

CPC分类号： G11C7/10 ,  G11C5/025 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.