公开(公告)号：US20190146687A1

公开(公告)日：2019-05-16

申请号：US16039342

申请日：2018-07-19

Applicant: Silicon Motion Inc.

Inventor： Jieh-Hsin Chien ,  Yi-Hua Pao

IPC: G06F3/06

Abstract: A method for performing refresh management in a memory device, the memory device and controller thereof are provided. The method may include: monitoring a temperature of the memory device, wherein the temperature is detected through a temperature sensor; updating a recorded highest temperature and a recorded lowest temperature according to said temperature; checking whether a difference between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference is greater than the predetermined temperature threshold, triggering refresh of the memory device.

公开(公告)号：US10289487B2

公开(公告)日：2019-05-14

申请号：US15495993

申请日：2017-04-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F11/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52 ,  G11C16/08

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

公开(公告)号：US10283216B2

公开(公告)日：2019-05-07

申请号：US15649394

申请日：2017-07-13

Applicant: Silicon Motion, Inc.

Inventor： Ching-Ke Chen ,  Po-Sheng Chou ,  Yang-Chih Shen

IPC: G11C29/52 ,  G11C29/04 ,  G11C29/42 ,  G06F11/10 ,  H03M13/00

Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read.

公开(公告)号：US10275163B2

公开(公告)日：2019-04-30

申请号：US15820727

申请日：2017-11-22

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen Shih ,  Yen-Hung Chen

IPC: G06F13/10 ,  G06F3/06 ,  G06F9/4401 ,  G06F13/42

Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.

公开(公告)号：US10248526B2

公开(公告)日：2019-04-02

申请号：US15662838

申请日：2017-07-28

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin

IPC: G06F11/30 ,  G06F12/02 ,  G06F3/06 ,  G11C16/10

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of blocks, and the blocks include a current block and temporary block. The controller writes a first data sector corresponding to a first logical address into the current block, and determines whether the temporary block has a second data sector that also corresponds to the first logical address, wherein when the temporary block already has a second data sector corresponding to the first logical address, the controller writes a first temporary-block table into the temporary block.

公开(公告)号：US20190095276A1

公开(公告)日：2019-03-28

申请号：US16039767

申请日：2018-07-19

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin ,  Yu-Da Chen

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52 ,  G06F3/06

Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. Each memory block includes multiple pages. The controller is coupled to the memory device and includes an ECC engine configured to check and correct errors that have occurred in data stored in the memory blocks. When a number of error bits in a page of one of the memory blocks exceeds a threshold, the controller is configured to add a block number of the memory block in a predetermined queue and when a garbage collection procedure has been triggered, the controller is configured to perform garbage collection on the memory block.

公开(公告)号：US20190089374A1

公开(公告)日：2019-03-21

申请号：US16194374

申请日：2018-11-18

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Jian-Dong Du

IPC: H03M13/11 ,  H03M13/37 ,  H03M13/45

Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.

公开(公告)号：US10236908B2

公开(公告)日：2019-03-19

申请号：US15495992

申请日：2017-04-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/00 ,  G11C16/10 ,  G11C11/56 ,  G11C16/26

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US20190079673A1

公开(公告)日：2019-03-14

申请号：US16190994

申请日：2018-11-14

Applicant: Silicon Motion, Inc.

Inventor： Chin-Pang Chang ,  Chun-Yi Lo

IPC: G06F3/06 ,  G06F1/08 ,  G06F1/12 ,  G06F12/02 ,  G06F1/04

CPC classification number: G06F3/061 ,  G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7208

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

公开(公告)号：US20190065361A1

公开(公告)日：2019-02-28

申请号：US15865269

申请日：2018-01-09

Applicant: Silicon Motion Inc.

Inventor： Jen-Hung Liao ,  Chia-Chin Hsieh

IPC: G06F12/02 ,  G11C16/08 ,  G11C16/10 ,  G11C16/04 ,  G11C29/52 ,  G06F3/06

Abstract: The present invention provides a method for writing data into a flash memory module, wherein each flash memory chip within the flash memory module includes a plurality of blocks, each block includes a plurality of pages, and the method includes: building a page-status table, wherein the page-status table records if at least a portion of pages within a specific block is/are damaged; when the data is to be written into the specific block, referring to the page-status table to determine if a specific page, which the data is intended to be written, is damaged; when the page-status table indicates that the specific page is not damaged, writing the data into the specific page; and when the page-status table indicates that the specific page is not damaged, not writing data into the specific page.