公开(公告)号：US06916713B2

公开(公告)日：2005-07-12

申请号：US10065646

申请日：2002-11-05

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/76

CPC classification number: H01L27/112 ,  H01L27/1126

Abstract: The present invention provides a code implantation process for the mask read only memory (MROM). A gate oxide layer and a wordline are formed sequentially over a substrate having a buried bitline, with a cap layer formed on the top of the wordline. A dielectric layer is formed on the substrate that is not covered by the wordline and the cap layer. A resist layer with a line/space pattern is formed on the dielectric layer and the cap layer, while the line/space pattern has a first extending direction different to a second extending direction of the cap layer. After removing the cap layer not covered by the resist layer, a code mask layer is formed over the substrate. An ion implantation step is performed to implant dopants into a predetermined code channel region by using the code mask layer, the dielectric layer and the remained cap layer as a mask.

Abstract translation: 本发明提供了一种用于掩模只读存储器（MROM）的代码注入过程。 在具有掩埋位线的衬底上顺序地形成栅极氧化物层和字线，其中盖层形成在字线的顶部。 在基板上形成介质层，该绝缘层未被字线和盖层覆盖。 在电介质层和盖层上形成具有线/空间图案的抗蚀剂层，而线/空间图案具有与盖层的第二延伸方向不同的第一延伸方向。 在除去未被抗蚀剂层覆盖的盖层之后，在衬底上形成码屏蔽层。 执行离子注入步骤，通过使用代码掩模层，电介质层和剩余帽层作为掩模将掺杂剂注入到预定的码信道区域中。

公开(公告)号：US20050009341A1

公开(公告)日：2005-01-13

申请号：US10249559

申请日：2003-04-18

Applicant: Ching-Yu Chang ,  Hsin-Huei Chen ,  Meng-Wei Chen

Inventor： Ching-Yu Chang ,  Hsin-Huei Chen ,  Meng-Wei Chen

IPC: G03F1/14 ,  H01L21/302 ,  H01L21/461

CPC classification number: G03F1/70

Abstract: A method of reducing a critical dimension (“CD”) bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dense pattern has a first opaque pattern and the isolation pattern has a second opaque pattern. The second step of the method is forming a virtual pattern around the isolation pattern, in which a distance between the virtual pattern and the isolation pattern is y, and the virtual pattern has a pattern line width x. By forming the virtual pattern around the isolation pattern, the flare effect of the isolation pattern is close to that of the dense pattern, thus the CD bias between a dense pattern, and an isolation pattern is reduced, and the process window does not shrink.

Abstract translation: 公开了一种降低致密图案和隔离图案之间的临界尺寸（“CD”）偏压的方法。 该方法包括提供具有致密图案的掩模，隔离图案和掩模的另一区域是透明的第一步骤，其中密集图案具有第一不透明图案，并且隔离图案具有第二不透明图案。 该方法的第二步是在隔离图案周围形成虚拟图案，其中虚拟图案和隔离图案之间的距离为y，虚拟图案具有图案线宽度x。 通过在隔离图案周围形成虚拟图案，隔离图案的耀斑效应接近密集图案的闪光效果，因此减小密集图案和隔离图案之间的CD偏差，并且处理窗口不缩小。

公开(公告)号：US06835504B2

公开(公告)日：2004-12-28

申请号：US10144893

申请日：2002-05-13

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: G03F900

CPC classification number: G03F1/50

Abstract: A photomask is constructed to include a substrate, a transmission control layer, and a reflective layer. The photomask may be used to pattern a photoresist layer deposited during the manufacturing process of semiconductor integrated circuits, and may be particularly useful for patterning photoresist layers in situations where the density of the structures varies across the photoresist layer and thus varies across the corresponding pattern on the photomask. The photomask can compensate for the different structural densities by adjusting the thickness of the transmission control layer. Areas of the photomask that have a lower structural density and therefore have a higher light intensity can be formed to have a thicker transmission control layer as compared to areas which have a higher structural density and which already have a lower light intensity.

Abstract translation: 光掩模被构造成包括衬底，透射控制层和反射层。 光掩模可以用于对在半导体集成电路的制造过程期间沉积的光致抗蚀剂层进行图案化，并且可以特别适用于在光致抗蚀剂层上的结构的密度变化并且因此在 光掩模 光掩模可以通过调节传输控制层的厚度来补偿不同的结构密度。 与具有较高结构密度且已经具有较低光强度的区域相比，具有较低结构密度并因此具有较高光强度的光掩模的区域可以形成为具有较厚的透射控制层。

公开(公告)号：US06734064B2

公开(公告)日：2004-05-11

申请号：US10248834

申请日：2003-02-24

Applicant: Tahorng Yang ,  Henry Chung ,  Cheng-Chen Calvin Hsueh ,  Ching-Yu Chang

Inventor： Tahorng Yang ,  Henry Chung ,  Cheng-Chen Calvin Hsueh ,  Ching-Yu Chang

IPC: H01L21336

CPC classification number: H01L27/1126 ,  H01L27/105 ,  H01L27/11293 ,  Y10S438/949

Abstract: A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.

Abstract translation: 只读存储器的制造方法提供具有存储单元区域和外围电路区域的衬底。 存储单元区域具有存储单元阵列，并且外围电路区域具有晶体管。 在存储单元区域中形成具有多个第一开口的精确层。 第一开口在存储单元阵列中的每个存储单元的沟道区之上，并且第一开口的临界尺寸相同。 在基板上形成具有第二开口和第三开口的掩模层。 第二开口位于预编码存储单元区域上，并且第三开口位于晶体管栅极之上。 执行离子注入以对预编码存储单元区域中的存储单元进行编码，并使用精确层和掩模层作为掩模来调节晶体管的阈值电压。

公开(公告)号：US06720210B1

公开(公告)日：2004-04-13

申请号：US10065431

申请日：2002-10-17

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L2182

CPC classification number: H01L27/11246 ,  H01L27/112 ,  H01L27/1126

Abstract: A mask read-only-memory structure and its method of manufacture are provided. The structure includes a substrate, a buried bit line in the substrate and a patterned stack layer covering a portion of the upper surface of the substrate. The stack layer includes a first dielectric layer, a stopping layer and a second dielectric layer. A gate oxide layer covers a portion of the upper surface of the substrate. A word line runs across the buried bit line to form a plurality of coding cells. The memory cells having a stack layer thereon are at a logic state “0” while the memory cells having a gate oxide layer thereon are at a logic state “1”.

Abstract translation: 提供了一种掩模只读存储器结构及其制造方法。 该结构包括衬底，衬底中的掩埋位线和覆盖衬底的上表面的一部分的图案化叠层。 堆叠层包括第一介电层，阻挡层和第二介电层。 栅极氧化物层覆盖衬底的上表面的一部分。 字线穿过掩埋位线，以形成多个编码单元。 其上具有堆叠层的存储单元处于逻辑状态“0”，而其上具有栅极氧化层的存储单元处于逻辑“1”。

公开(公告)号：US06670103B2

公开(公告)日：2003-12-30

申请号：US10136437

申请日：2002-05-02

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L213215

CPC classification number: H01L27/11253 ,  H01L21/266

Abstract: A method for forming a lightly doped diffusion region comprises providing a substrate structure. A first photoresist layer, having a lightly doped diffusion region pattern, is formed on the substrate structure. Next, dopants of a first type conductivity are implanted into the substrate structure for forming a lightly doped diffusion region in the substrate structure. Then a second photoresist layer is conformal formed on the first photoresist layer and the substrate structure. Next, the second photoresist layer is etched back and then dopants of a second type conductivity are implanted into the substrate structure for forming a source/drain region underlying the lightly doped diffusion region in the substrate structure.

公开(公告)号：US06576515B2

公开(公告)日：2003-06-10

申请号：US09727154

申请日：2000-11-30

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L21336

CPC classification number: H01L21/28273 ,  H01L29/42324

Abstract: A method of forming a transistor gate. A substrate having a source/drain terminals, a gate dielectric layer, a lower section of a floating gate, a dielectric layer over the substrate is provided. The dielectric layer has an opening that exposes a portion of the upper surface of the lower section of the floating gate. A conductive material layer having slant exterior sidewalls is formed over the dielectric layer. The conductive material layer fills the via opening completely. A mask material layer is formed over the conductive layer. A mask material layer is formed over the conductive layer. A planarization is carried out to remove a portion of the mask material layer, thereby forming an etching mask layer that exposes the upper surface of the conductive layer. Using the etching mask layer as a mask, an anisotropic slant etching is carried out to etch the conductive layer to a predefined depth so that an opening in the upper section of the floating gate is formed. The etching mask layer is then removed. An inter-gate dielectric layer and a control gate layer are sequentially formed over the upper section of the floating gate to form a complete gate structure.

公开(公告)号：US06548384B2

公开(公告)日：2003-04-15

申请号：US09854959

申请日：2001-05-14

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L2122

CPC classification number: G03F7/095 ,  G03F7/094 ,  H01L21/0274

Abstract: A method for performing lithographic process to a multi-layered photoresist layer. The method at least includes the following steps. First of all, a substrate is provided. Then, a first photoresist film is formed on the substrate, and a mask layer is formed on the first photoresist film, wherein the mask layer is different from the first photoresist film. Next, a second photoresist film is formed on the mask layer, and a pattern is transferred into the second photoresist film by using lithographic process. Then, the mask layer is etched by using the second photoresist film as a first mask such that the pattern is transferred into layer. Finally, the pattern is transferred into the first photoresist film by using the mask layer as a second mask.

公开(公告)号：US06541828B2

公开(公告)日：2003-04-01

申请号：US09939982

申请日：2001-08-23

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L2976

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method of fabricates a non-volatile ROM device on a semiconductor substrate with a plurality of parallel buried bit lines, a gate oxide layer above the substrate and word lines formed above the gate oxide layer comprises: forming a dielectric layer over the word lines and gate oxide layer, forming and pattern first photoresist layer over the dielectric layer, etching the dielectric layer, stripping the first photoresist layer, forming and pattern second photoresist layer over the dielectric layer to develop an opening area for ion implantation, ion implanting a code implant dopant through the opening area down into the substrate and stripping the second photoresist layer.

Abstract translation: 一种在具有多个并行掩埋位线的半导体衬底上制造非易失性ROM器件的方法，在衬底上方的栅极氧化层和形成在栅极氧化物层上方的字线​​包括：在字线之上形成介电层， 栅极氧化物层，在电介质层上形成和图案化第一光致抗蚀剂层，蚀刻电介质层，剥离第一光致抗蚀剂层，在电介质层上形成和图案化第二光致抗蚀剂层，以形成用于离子注入的开口区域， 掺杂剂通过开口区域向下进入衬底并剥离第二光致抗蚀剂层。

公开(公告)号：US06534407B2

公开(公告)日：2003-03-18

申请号：US09871663

申请日：2001-06-04

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L21302

CPC classification number: B24B37/013 ,  B24B37/042 ,  H01L21/31053 ,  H01L21/76224

Abstract: A method for reducing dishing effects is provided. The method is applied to polish a surface of a wafer containing a silicate film thereon. The method comprises using a polishing slurry containing organic alkyl or aryl compound with at least one hydroxyl group (i.e. ROH compound) during the process of polishing the silicate film. An organic hydrophobic layer created over the silicate film in contact with the ROH compound thus alleviates the undesirable dishing effects. The organic hydrophobic layer is thereafter cleaned using ozone-containing deionized water.