公开(公告)号：US11095012B2

公开(公告)日：2021-08-17

申请号：US16329587

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/16 ,  H01P11/00 ,  H01P3/12 ,  H01Q9/04 ,  H04L29/08

Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.

公开(公告)号：US11016288B2

公开(公告)日：2021-05-25

申请号：US16072161

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Feras Eid ,  Johanna M. Swan ,  Thomas L. Sounart ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Baris Bicen ,  Valluri R. Rao

IPC: G02B26/08 ,  H01L27/20 ,  H01L41/09 ,  H01L41/253

Abstract: Embodiments of the invention include a display formed on an organic substrate and methods of forming such a device. According to an embodiment, an array of pixel mirrors may be formed on the organic substrate. For example, each of the pixel mirrors is actuatable about one or more axes out of the plane of the organic substrate. Additionally, embodiments of the invention may include an array of routing mirrors formed on the organic substrate. According to an embodiment, each of the routing mirrors is actuatable about two axes out of the plane of the organic substrate. In embodiments of the invention, a light source may be used for emitting light towards the array of routing mirrors. For example, light emitted from the light source may be reflected to one or more of the pixel mirrors by one of the routing mirrors.

公开(公告)号：US20210111170A1

公开(公告)日：2021-04-15

申请号：US17129134

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20210111155A1

公开(公告)日：2021-04-15

申请号：US17129095

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/544

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20210111147A1

公开(公告)日：2021-04-15

申请号：US17126884

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20210111124A1

公开(公告)日：2021-04-15

申请号：US17128380

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US10820437B2

公开(公告)日：2020-10-27

申请号：US16335050

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Son V. Nguyen ,  Rajat Goyal ,  David B. Lampner ,  Dilan Seneviratne ,  Albert S. Lopez ,  Joshua D. Heppner ,  Srinivas V. Pietambaram ,  Shawna M. Liff ,  Nadine L. Dabby

IPC: G06F17/30 ,  H05K5/06 ,  H05K5/00 ,  H05K5/02 ,  G06F1/18 ,  G06F1/16 ,  G04G17/04

Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.

公开(公告)号：US10790231B2

公开(公告)日：2020-09-29

申请号：US16510295

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

公开(公告)号：US10748844B2

公开(公告)日：2020-08-18

申请号：US15859331

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Shawna M. Liff

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  G02B6/122 ,  G02B6/12 ,  G02B6/42

Abstract: Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.

公开(公告)号：US10734358B2

公开(公告)日：2020-08-04

申请号：US16008457

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Jonathan L. Rosch ,  Amruthavalli Pallavi Alur ,  Arun Chandrasekhar ,  Shawna M. Liff

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/492 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00 ,  H01L23/495

Abstract: Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.