公开(公告)号：US20210183873A1

公开(公告)日：2021-06-17

申请号：US16711884

申请日：2019-12-12

Applicant: Micron Technology, Inc.

Inventor： Robert B. Goodwin ,  Sanh D. Tang

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/108 ,  G11C11/22

Abstract: Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210151440A1

公开(公告)日：2021-05-20

申请号：US17159719

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kirk D. Prall ,  Mitsunari Sukekawa

IPC: H01L27/108

Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

公开(公告)号：US10998440B2

公开(公告)日：2021-05-04

申请号：US16596407

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Ramanathan Gandhi ,  Hong Li ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Sanh D. Tang ,  Scott E. Sills

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.

公开(公告)号：US10991759B2

公开(公告)日：2021-04-27

申请号：US15497032

申请日：2017-04-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Sanh D. Tang ,  David H. Wells

IPC: H01L27/24 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00 ,  H01L21/8234 ,  H01L29/45

Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

公开(公告)号：US20210057424A1

公开(公告)日：2021-02-25

申请号：US16549519

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20210013226A1

公开(公告)日：2021-01-14

申请号：US17028734

申请日：2020-09-22

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Richard J. Hill ,  Yi Fang Lee ,  Martin C. Roberts

IPC: H01L27/11582 ,  H01L27/11585 ,  H01L27/11514 ,  G06F3/06

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

公开(公告)号：US10886278B2

公开(公告)日：2021-01-05

申请号：US16578608

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Sanh D. Tang

IPC: H01L21/20 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532 ,  H01L29/423 ,  H01L29/08

Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias individually having an upper horizontal perimeter. The conductive vias individually have an upper horizontal perimeter. Masking material is formed directly above the conductive vias. An opening is formed in the masking material directly above individual of the upper horizontal perimeters of individual of the conductive vias. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Conductive material is formed in the individual masking-material openings against sidewalls of the individual masking-material openings and directly against the conductive via directly there-below. An upper horizontal perimeter of the conductive material in the individual masking-material openings extends outwardly beyond the upper horizontal perimeter of the conductive via directly there-below.

公开(公告)号：US10818667B2

公开(公告)日：2020-10-27

申请号：US16521801

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Silvia Borsari ,  Sau Ha Cheung

IPC: H01L27/108 ,  H01L21/02 ,  H01L23/528

Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars. Wordlines are formed within the trenches and along the pillars.

公开(公告)号：US20200235103A1

公开(公告)日：2020-07-23

申请号：US16831355

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Amirhasan Nourbakhsh ,  John K. Zahurak ,  Sanh D. Tang ,  Silvia Borsari ,  Hong Li

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10607851B2

公开(公告)日：2020-03-31

申请号：US15686526

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Andrew L. Li ,  Prashant Raghu ,  Sanjeev Sapra ,  Rita J. Klein ,  Sanh D. Tang ,  Sourabh Dhir

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L21/66 ,  H01L21/67 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.