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公开(公告)号：US20190334530A1
公开(公告)日：2019-10-31
申请号：US15966134
申请日：2018-04-30
Applicant: STMicroelectronics International N.V.
Inventor： Nitin GUPTA , Kapil Kumar TYAGI
Abstract: A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.
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公开(公告)号：US20190317851A1
公开(公告)日：2019-10-17
申请号：US16454365
申请日：2019-06-27
Inventor： Om RANJAN , Riccardo GEMELLI , Abhishek GUPTA
Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
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223.发明授权公开(公告)号：US10425173B2
公开(公告)日：2019-09-24
申请号：US15988055
申请日：2018-05-24
Applicant: STMicroelectronics International N.V.
Inventor： Nicolas Cordier
Abstract: A method for a phase calibration in a frontend circuit of a near field communication (NFC) tag device is disclosed. An active load modulation signal is generated with a preconfigured value of a phase difference with respect to a reference signal of an NFC signal generator device. An amplitude of a test signal present at an antenna of the NFC tag device is measured. The test signal results from overlaying of the reference signal with the active load modulation signal. The following steps are repeated: modifying the value of the phase difference, providing the active load modulation signal with the modified value of the phase difference, measuring an amplitude of the test signal and comparing the measured amplitude with the previously measured amplitude until the measured amplitude fulfills a predefined condition. The value of the phase difference corresponding to the previously measured amplitude is stored.
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公开(公告)号：US10402527B2
公开(公告)日：2019-09-03
申请号：US15423289
申请日：2017-02-02
Inventor： Thomas Boesch , Giuseppe Desoli
Abstract: Embodiments are directed towards a reconfigurable stream switch formed in an integrated circuit. The stream switch includes a plurality of output ports, a plurality of input ports, and a plurality of selection circuits. The output ports each have an output port architectural composition, and each is arranged to unidirectionally pass output data and output control information. The input ports each have an input port architectural composition, and each is arranged to unidirectionally receive first input data and first input control information. Each one of the selection circuits is coupled to an associated one of the output ports. Each selection circuit is further coupled to all of the input ports such that each selection circuit is arranged to reconfigurably couple its associated output port to no more than one input port at any given time.
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225.发明授权公开(公告)号：US10348539B1
公开(公告)日：2019-07-09
申请号：US15919745
申请日：2018-03-13
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha
IPC: H04L27/06 , H04L27/16 , H04L27/00 , H04L27/14 , H04L27/156
Abstract: A frequency demodulated signal includes a frequency modulation in time that is shifted by a DC level corresponding to a carrier frequency offset. A number of different frequency offsets are applied to the frequency demodulated signal to generate a corresponding number of offset frequency demodulated signals. Each offset frequency demodulated signal is correlated against a reference signal and a determination is made as to which correlation produces a highest correlation value. One offset frequency demodulated signal of the number of offset frequency demodulated signals is then selected for output as an offset corrected frequency demodulated signal. The selected signal is the one having the highest correlation value.
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Patent Agency Ranking
226.发明授权公开(公告)号：US10333397B2
公开(公告)日：2019-06-25
申请号：US15652748
申请日：2017-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Abhishek Mittal
IPC: H02M3/07
Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.
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公开(公告)号：US10311944B2
公开(公告)日：2019-06-04
申请号：US16025647
申请日：2018-07-02
Applicant: STMicroelectronics International N.V.
Inventor： Dhori Kedar Janardan , Abhishek Pathak , Shishir Kumar
IPC: G11C5/06 , G11C11/417
Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.
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公开(公告)号：US10298119B2
公开(公告)日：2019-05-21
申请号：US15806023
申请日：2017-11-07
Applicant: STMICROELECTRONICS INTERNATIONAL N.V
Inventor： Phalguni Bala , Hiten Advani
Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.
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公开(公告)号：US10296822B2
公开(公告)日：2019-05-21
申请号：US15894440
申请日：2018-02-12
Applicant: STMicroelectronics International N.V.
Inventor： Vinko Kunc , Anton Stern , Kosta Kovacic , Albin Pevec , Maksimiljan Stiglic
IPC: G06K19/07 , G06K19/077
Abstract: An RFID transponder device has antenna terminals for coupling an antenna system to the device. A transmitter and a receiver are coupled to the antenna terminals. The device has at least one damping resistance connected to at least one of the antenna terminals. The at least one damping resistance is connected, depending on a voltage swing at the antenna terminals during a transmission burst period, either together with a serially connected switch in parallel to the antenna terminals that are coupled to the receiver, or together with a parallel connected switch between one of the antenna terminals and a terminal of the transmitter. A damping control is configured to activate the at least one damping resistance during a damping period after the transmission burst period by controlling the respective switch.
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公开(公告)号：US10295416B2
公开(公告)日：2019-05-21
申请号：US15289360
申请日：2016-10-10
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Nitin Bansal
Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor at varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.
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