公开(公告)号：US20190065332A1

公开(公告)日：2019-02-28

申请号：US16016089

申请日：2018-06-22

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE ,  Guan-Yao HUANG ,  Shen-Ting CHIU

IPC: G06F11/20 ,  G06F3/06

Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of planes, and each plane includes a plurality of blocks. A portion of blocks in each of the planes constitutes a super block, so that the flash memory includes a plurality of super blocks. The controller is coupled to the flash memory. When a first block of at least one first super block of the super blocks is damaged, and a second block of a second super block in the position corresponding to the damaged block is normal, the controller merges the second block of the second super block with the first super block to replace the first block. The random-access memory stores a compression table to record position information about the first block in the first super block and the number information of the second block.

公开(公告)号：US20190065308A1

公开(公告)日：2019-02-28

申请号：US15863893

申请日：2018-01-06

Applicant: Silicon Motion, Inc.

Inventor： Tai-Hao YEH

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of planes, and each of the planes includes a plurality of blocks. Each of the blocks includes a plurality of pages. The size of each page is N K-bytes, wherein N is a positive integer greater than 1. The controller is coupled to the flash memory to calculate the ECC bit number of each page using a detection unit of 1 Kbyte. The controller statistically calculates the number of detection units of the pages corresponding to different values of the ECC bit number in order to determine whether each plane of the flash memory is normal or not.

公开(公告)号：US20190065305A1

公开(公告)日：2019-02-28

申请号：US15865266

申请日：2018-01-09

Applicant: Silicon Motion Inc.

Inventor： Hung-En Hsieh ,  Che-Yi Wu

IPC: G06F11/10 ,  H03M13/09 ,  G06F12/02 ,  G06F3/06

Abstract: A method for performing data processing for error handling in a memory device, the memory device and the controller thereof, and the associated electronic device are provided. The method may include: programming a codeword of a set of data into a non-volatile (NV) memory, wherein the codeword includes the set of data and a parity-check code; reading the codeword from a volatile memory to generate readout data of the codeword; determining whether the readout data is correct according to the readout version of the set of data and the readout version of the parity-check code; and when determining that the readout data is correct, outputting the readout version of the set of data as the set of data for further usage of the processing circuit, otherwise, sending a predetermined signal to the processing circuit and storing error information regarding the set of data into a register of the controller.

公开(公告)号：US20190050167A1

公开(公告)日：2019-02-14

申请号：US15922669

申请日：2018-03-15

Applicant: Silicon Motion, Inc.

Inventor： Ming-Chang Hsieh ,  Che-Wei Hsu ,  Wen-Chi Hong

IPC: G06F3/06 ,  G06F9/38 ,  G06F11/14 ,  G06F11/10

Abstract: A storage device receiving an external instruction from a host includes a plurality of flash memory spaces and a controller. The controller receives the external instruction, queues the external instruction in a first command queue, translates the external instruction into a plurality of operation commands, and sequentially executes the operation commands to respectively operate the flash memory spaces. The controller further gives an identity code to at least one specific operation command to track the execution result of the specific operation command.

公开(公告)号：US10199110B2

公开(公告)日：2019-02-05

申请号：US15852847

申请日：2017-12-22

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/10

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

公开(公告)号：US20190027214A1

公开(公告)日：2019-01-24

申请号：US16127240

申请日：2018-09-11

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26

Abstract: A Flash memory access module performs memory access management of a Flash storage device including a plurality of storage cells. The Flash memory access module includes: a read only memory for storing a program code; and a microprocessor which executes the program code to perform the following steps: performing a first sensing operation corresponding to a first sensing voltage in a storage cell, and performing a second sensing operation in the storage cell; using the first sensing operation and at least the second sensing operation to generate a first digital value and a second digital value, respectively, of the storage cell; using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

公开(公告)号：US20190013292A1

公开(公告)日：2019-01-10

申请号：US15869816

申请日：2018-01-12

Applicant: Silicon Motion, Inc.

Inventor： Shu-Ying HUANG ,  Te-Wei CHEN ,  Hsiu-Yuan CHEN

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/66

Abstract: The invention introduces a method for wire bonding and testing, performed by wire-bonding equipment, including at least the following steps: providing a substrate and dies, where the substrate has exposed fingers and each die has exposed pads; controlling a motor to hold the substrate by a metal frame, where all the exposed fingers are floating from the metal frame to avoid ESD (electrostatic discharge) fail; and performing a wire bonding to make interconnections between the pads on the dies and the fingers on the substrate to fabricate a semi-finished flash-memory product.

公开(公告)号：US20190007168A1

公开(公告)日：2019-01-03

申请号：US16013121

申请日：2018-06-20

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen SHIH

IPC: H04L1/00 ,  G06F11/10 ,  H04L1/16 ,  H04L1/20 ,  G06F13/16

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.

公开(公告)号：US10168913B2

公开(公告)日：2019-01-01

申请号：US15618224

申请日：2017-06-09

Applicant: Silicon Motion, Inc.

Inventor： Chien-Cheng Lin ,  Jie-Hao Lee

IPC: G06F3/06 ,  G06F12/02

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

公开(公告)号：US20180341578A1

公开(公告)日：2018-11-29

申请号：US15853453

申请日：2017-12-22

Applicant: Silicon Motion, Inc.

Inventor： Chiu-Han CHANG

IPC: G06F12/02 ,  G06F3/06

Abstract: A data storage device utilized for storing a plurality of data, wherein the data storage device includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory and maps the logical pages to the physical pages of the memory, and it performs a leaping linear search for the logical pages. The controller searches the Nth logical page of the logical pages according to a predetermined value N. N is a positive integer greater than 1. When the Nth logical page is a currently-used logical page, the controller incrementally decreases the predetermined value N to keep searching the logical pages until a non-currently-used logical page is detected.