公开(公告)号：US07196374B1

公开(公告)日：2007-03-27

申请号：US10653274

申请日：2003-09-03

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

公开(公告)号：US07183152B1

公开(公告)日：2007-02-27

申请号：US10975475

申请日：2004-10-29

Applicant: Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/00 ,  H01L21/84 ,  H01L21/3205

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687

Abstract: A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method includes growing a second material in the trench to form the fin and removing the layer of first material.

Abstract translation: 形成鳍状场效应晶体管（FinFET）的鳍片的方法包括在第一材料层中限定沟槽，其中沟槽的开口的宽度基本上小于该层的厚度。 该方法包括在沟槽中生长第二材料以形成翅片并去除第一材料层。

公开(公告)号：US07112847B1

公开(公告)日：2006-09-26

申请号：US10653227

申请日：2003-09-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  Y10S257/90

Abstract: A semiconductor device includes a semiconductor fin formed on an insulator and sidewall spacers formed adjacent the sides of the fin. A gate material layer is formed over the fin and the sidewall spacers and etched to form a gate. The presence of the sidewall spacers causes a topology of the gate material layer to smoothly transition over the fin and the first and second sidewall spacers.

Abstract translation: 半导体器件包括形成在绝缘体上的半导体鳍片和邻近翅片侧面形成的侧壁间隔物。 栅极材料层形成在鳍片和侧壁间隔物上并被蚀刻以形成栅极。 侧壁间隔物的存在导致栅极材料层的拓扑结构平滑地过渡翅片和第一和第二侧壁间隔物。

公开(公告)号：US20060147617A1

公开(公告)日：2006-07-06

申请号：US11176261

申请日：2005-07-08

Applicant: Pin-Chen Chen ,  Hui-Lung Kuo ,  Chih-Ho Chiu ,  Liang-Bin Yu

Inventor： Pin-Chen Chen ,  Hui-Lung Kuo ,  Chih-Ho Chiu ,  Liang-Bin Yu

IPC: B05D5/06

CPC classification number: G02B5/201

Abstract: A color filter having a bi-layer metal grating is formed by nanoimprint lithography. Nanoimprint lithography, a low cost technology, includes two alternatives, i.e., hot-embossing nanoimprint lithography and UV-curable nanoimprint lithography. Manufacture steps comprises providing a substrate with a polymer material layer disposed thereon. A plurality of lands and grooves are formed in the polymer material layer, and a first metal layer and a second metal layer are disposed on the surfaces of the lands and grooves, respectively. Finally, a color filter having a bi-layer metal grating is obtained.

Abstract translation: 具有双层金属光栅的滤色器通过纳米压印光刻形成。 低成本技术的纳米压印光刻技术包括两种替代方案，即热压印纳米压印光刻和UV可固化纳米压印光刻。 制造步骤包括提供其上设置有聚合物材料层的基底。 在聚合物材料层中形成多个焊盘和沟槽，并且第一金属层和第二金属层分别设置在焊盘和焊盘的表面上。 最后，获得具有双层金属光栅的滤色器。

公开(公告)号：US07041601B1

公开(公告)日：2006-05-09

申请号：US10653103

申请日：2003-09-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L21/311

CPC classification number: H01L29/7842 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a MOSFET type semiconductor device includes forming a fin structure and a dummy gate structure over the fin structure. Sidewall spacers may be formed adjacent the dummy gate structure. The dummy gate structure may be later removed and replaced with a metal layer that is formed at a high temperature (e.g., 600°–700° C.). The cooling of the metal layer induces strain to the fin structure that affects the mobility of the double-gate MOSFET.

Abstract translation: 制造MOSFET型半导体器件的方法包括在鳍结构上形成翅片结构和虚拟栅极结构。 侧壁间隔件可以与伪栅极结构相邻地形成。 可以稍后去除虚拟栅极结构并用在高温（例如600℃-700℃）下形成的金属层代替。 金属层的冷却会引起对鳍结构的应变，从而影响双栅极MOSFET的迁移率。

公开(公告)号：US20060089820A1

公开(公告)日：2006-04-27

申请号：US10973186

申请日：2004-10-25

Applicant: Bin Yu ,  Yong Rui

Inventor： Bin Yu ,  Yong Rui

IPC: G06F11/30 ,  G21C17/00 ,  G06F15/00

CPC classification number: G06Q10/10

Abstract: An event-based system and process for recording and playback of collaborative electronic presentations is presented. The present system and process includes a technique for recording collaborative electronic presentations by capturing and storing the interactions between each participant and presentation data where each interaction event is timestamped and linked to a data file comprising the presentation data. The present system and process also includes a technique for playing back the recorded collaborative electronic presentation, which involves displaying the presentation data in an order it was originally presented and reproducing the recorded interactions between each participant and the displayed presentation data at the same point in the presentation that they were originally performed, based on the aforementioned timestamps.

公开(公告)号：US07019363B1

公开(公告)日：2006-03-28

申请号：US09476961

申请日：2000-01-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66659

Abstract: A method of fabricating an integrated circuit utilizes symmetric source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS). The drain extension is deeper than the source extension. The source extension is more conductive than the drain extension. The transistor has reduced short channel effects and strong drive current and yet is reliable.

Abstract translation: 一种制造集成电路的方法采用对称的源极/漏极结。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。 漏极扩展比源扩展更深。 源极延伸比漏极延伸更为导电。 晶体管减少了短沟道效应和强大的驱动电流，而且可靠。

公开(公告)号：US06998301B1

公开(公告)日：2006-02-14

申请号：US10653225

申请日：2003-09-03

Applicant: Bin Yu ,  Shibly S. Ahmed

Inventor： Bin Yu ,  Shibly S. Ahmed

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/02672 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/2022 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a tri-gate semiconductor device that includes a substrate and a dielectric layer formed on the substrate includes depositing a first dielectric layer on the dielectric layer and etching the first dielectric layer to form a structure. The method further includes depositing a second dielectric layer over the structure, depositing an amorphous silicon layer over the second dielectric layer, etching the amorphous silicon layer to form amorphous silicon spacers, where the amorphous silicon spacers are disposed on opposite sides of the structure, depositing a metal layer on at least an upper surface of each of the amorphous silicon spacers, annealing the metal layer to convert the amorphous silicon spacers to crystalline silicon fin structures, removing a portion of the second dielectric layer, depositing a gate material, and etching the gate material to form three gates.

Abstract translation: 一种形成三栅极半导体器件的方法，包括在衬底上形成的衬底和电介质层，包括在电介质层上沉积第一介电层并蚀刻第一介电层以形成结构。 该方法还包括在结构上沉积第二介电层，在第二介电层上沉积非晶硅层，蚀刻非晶硅层以形成非晶硅间隔物，其中非晶硅间隔物设置在结构的相对侧上，沉积 在每个非晶硅间隔物的至少上表面上的金属层，退火金属层以将非晶硅间隔物转化为晶体硅鳍结构，去除第二电介质层的一部分，沉积栅极材料，并蚀刻 门材料形成三门。

公开(公告)号：US06963104B2

公开(公告)日：2005-11-08

申请号：US10459576

申请日：2003-06-12

Applicant: Yider Wu ,  Bin Yu

Inventor： Yider Wu ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, a number of dielectric layers and a control gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The dielectric layers are formed over the fin and the control gate is formed over the dielectric layers. The dielectric layers may include oxide-nitride-oxide layers that function as a charge storage structure for the memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍片，多个电介质层和控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 电介质层形成在鳍片之上，并且控制栅极形成在电介质层上。 电介质层可以包括用作存储器件的电荷存储结构的氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06958512B1

公开(公告)日：2005-10-25

申请号：US10770010

申请日：2004-02-03

Applicant: Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/42324 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，导电结构和控制栅。 绝缘层可以形成在基板上，并且鳍可以形成在绝缘层上。 导电结构可以形成在鳍的一侧附近，并且控制栅可以形成在翅片上。 导电结构可以用作非易失性存储器件的浮栅电极。