公开(公告)号：US11296190B2

公开(公告)日：2022-04-05

申请号：US16743589

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L29/10 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/74

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.

公开(公告)号：US11289474B2

公开(公告)日：2022-03-29

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Halting Wang ,  Tung-Hsing Lee

IPC: H01L21/00 ,  H01L27/11 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20220093751A1

公开(公告)日：2022-03-24

申请号：US17029446

申请日：2020-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ketankumar H. Tailor ,  Peter Baars ,  Ruchil K. Jain

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49

Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.

公开(公告)号：US20220093744A1

公开(公告)日：2022-03-24

申请号：US17029667

申请日：2020-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Yves Ngu ,  Michael Zierak

IPC: H01L29/10 ,  H01L21/763 ,  H01L29/04 ,  H01L27/12

Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.

公开(公告)号：US20220091335A1

公开(公告)日：2022-03-24

申请号：US17026799

申请日：2020-09-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures for an optical power splitter/combiner and methods of forming a structure for an optical power splitter/combiner. A first waveguide core is positioned adjacent to a second waveguide core. The first waveguide core includes a first end surface and a first tapered section that tapers toward the first end surface. The second waveguide core includes a second end surface and a second tapered section that tapers toward the second end surface. A third waveguide core is positioned in a different level than the first waveguide core and the second waveguide core. The third waveguide core includes a third end surface and a third tapered section that tapers toward the third end surface. The third tapered section includes a portion laterally positioned between the first tapered section of the first waveguide core and the second tapered section of the second waveguide core.

公开(公告)号：US20220091331A1

公开(公告)日：2022-03-24

申请号：US17031032

申请日：2020-09-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng BIAN

IPC: G02B6/124

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to spiral waveguide absorbers and methods of manufacture. The structure includes: a photonics component; and a waveguide absorber with a grating pattern coupled to a node of the photonics component.

公开(公告)号：US11275207B2

公开(公告)日：2022-03-15

申请号：US16989214

申请日：2020-08-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/125 ,  G02B6/136 ,  G02B6/12

Abstract: Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A waveguide core has a first section, a second section, and a waveguide bend connecting the first section with the second section. The waveguide core includes a first side surface extending about an inner radius of the waveguide bend and a second side surface extending about an outer radius of the waveguide bend. A curved strip is arranged over the waveguide bend adjacent to the first side surface or the second side surface.

公开(公告)号：US11271077B2

公开(公告)日：2022-03-08

申请号：US16807453

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  John J. Pekarik ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L27/01 ,  H01L21/76 ,  H01L29/06 ,  H01L29/04 ,  H01L21/762 ,  H01L27/102 ,  H01L29/737 ,  H01L27/12 ,  H01L21/324 ,  H01L29/32

Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.

公开(公告)号：US20220059523A1

公开(公告)日：2022-02-24

申请号：US17001009

申请日：2020-08-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You LI ,  Alain F. LOISEAU ,  Souvick MITRA ,  Tsung-Che TSAI ,  Robert J. GAUTHIER, JR. ,  Meng MIAO

IPC: H01L27/02 ,  H01L29/73

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

公开(公告)号：US20220057445A1

公开(公告)日：2022-02-24

申请号：US17519742

申请日：2021-11-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Dewei Xu ,  Eric D. Hunt-Schroeder

IPC: G01R31/28

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.