公开(公告)号：US20030214596A1

公开(公告)日：2003-11-20

申请号：US10437741

申请日：2003-05-14

Applicant: STMICROELECTRONICS S.A.

Inventor： Laurent Simony

IPC: H04N005/335

CPC classification number: H04N5/363

Abstract: A low-noise CMOS active pixel for image sensors comprises a photosensitive element (PD), a feedback capacitive element (CF) with a capacitance CF, and four transistors, namely a first transistor (M1), two reset transistors (M3, M4) and one pixel selection transistor (M2). These components are laid out and controlled in such a way that the first transistor (M1) is mounted as an amplifier during the pixel reset phase and as a follower during the read phase. The reset transistors (M3, M4) are parallel-connected so that one of them (M4) compensates for the negative effects of the other transistor (M3) on the node common to the two transistors.

Abstract translation: 用于图像传感器的低噪声CMOS有源像素包括光敏元件（PD），具有电容CF的反馈电容元件（CF）和四个晶体管，即第一晶体管（M1），两个复位晶体管（M3，M4） 和一个像素选择晶体管（M2）。 这些部件被布置和控制，使得第一晶体管（M1）在像素复位阶段期间作为放大器安装，并且在读取阶段期间作为跟随器安装。 复位晶体管（M3，M4）并联，使得它们中的一个（M4）补偿两个晶体管共同的节点上的另一个晶体管（M3）的负面影响。

公开(公告)号：US20030207569A1

公开(公告)日：2003-11-06

申请号：US09858400

申请日：2001-05-16

Applicant: STMicroelectronics S.A. and Koninklijke Philips Electronics N.V.

Inventor： Eric Gerritsen ,  Bruno Baylac ,  Marie-Therese Basso

IPC: H01L021/44

CPC classification number: H01L29/66575 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract translation: 一种在硅半导体衬底的表面上形成低电阻率硅化钛层的工艺。 在该过程中，将有效量的诸如铟，镓，锡或铅的金属元素注入或沉积在硅衬底的表面上。 在硅衬底的表面上沉积钛层，并且执行钛涂覆的硅衬底的快速热退火以形成低电阻率硅化钛。 在优选的方法中，金属元素是铟或镓，更优选金属元素是铟。 还提供了在硅衬底的表面上具有硅化钛层的半导体器件。

公开(公告)号：US20030146468A1

公开(公告)日：2003-08-07

申请号：US10379169

申请日：2003-03-04

Applicant: STMicroelectronics S.A

Inventor： Yvon Gris ,  Thierry Schwartzmann

IPC: H01L029/788

CPC classification number: H01L27/0826 ,  H01L21/761 ,  H01L21/76232 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623

Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Abstract translation: 一种在P型衬底中制造双极晶体管的方法，包括以下步骤：在衬底中形成第一N型区域; 通过外延形成第一硅层; 在该第一层中形成，并且在第一区域上基本上在第二区域分离第二重掺杂P型区域; 在该第二区域的周围形成第三N型区域; 通过外延形成第二硅层; 形成穿过所述第一和第二硅层的深沟槽，穿过所述衬底并将所述第二区域与所述第三区域横向分开; 以及执行退火，使得第三区域的掺杂剂与第一区域的掺杂剂连续。

公开(公告)号：US20030126513A1

公开(公告)日：2003-07-03

申请号：US10317005

申请日：2002-12-11

Applicant: STMicroelectronics S.A.

Inventor： Sylvie Wuidart

IPC: H04B001/74

CPC classification number: G06F11/1008 ,  G06F11/08 ,  G11C16/22

Abstract: An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.

Abstract translation: 电可擦除和可编程的存储器包括至少一个不可擦除的安全区域。 在安全区域中读取错误的检测和/或校正是通过在安全区域中记录冗余位并且当在安全区域中读取的冗余位不相等时传送误差信号和/或具有多数值的位来提供的。

公开(公告)号：US20030112226A1

公开(公告)日：2003-06-19

申请号：US10292380

申请日：2002-11-12

Applicant: STMICROELECTRONICS S.A.

Inventor： Laurent Le-Pailleur

IPC: G09G005/00

CPC classification number: G06K9/0002 ,  G06F3/044 ,  G06F2203/0338

Abstract: A touch-sensitive detector includes a detection surface and a conducting element, and a first and second set of electrodes, each set of electrodes including at least one electrode extending parallel to the detection surface and where each electrode is electrically isolated. A first and second interaction capacitor is formed by the conducting element with the first and second set of electrodes, respectively. The second interaction capacitor has a lower capacitance than the first interaction capacitor. The touch-sensitive detection element further includes a first and second set of detectors arranged for detecting a signal emitted by at least one electrode of the first set of electrodes and the second set of electrodes, respectively, and transmitted through an external element located at the electrode emitting the signal. The external element contacts the detection surface. A touch sensitive detection method is also provided.

Abstract translation: 触敏检测器包括检测表面和导电元件，以及第一和第二组电极，每组电极包括平行于检测表面延伸的至少一个电极，并且每个电极电隔离。 第一和第二相互作用电容器分别由第一和第二组电极由导电元件形成。 第二相互作用电容器具有比第一相互作用电容器低的电容。 触敏检测元件还包括第一和第二组检测器，其被布置用于分别检测由第一组电极和第二组电极的至少一个电极发射的信号，并通过位于 电极发出信号。 外部元件接触检测表面。 还提供了触敏检测方法。

公开(公告)号：US20030081149A1

公开(公告)日：2003-05-01

申请号：US10280737

申请日：2002-10-25

Applicant: STMicroelectronics S.A.

Inventor： Diego Coste

IPC: H03L007/00 ,  H04N009/475

CPC classification number: H04N5/10 ,  H04N5/126

Abstract: A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.

Abstract translation: 同步过程可以包括检测视频信号的连续水平同步脉冲，以及连续检测到的脉冲之间的相位比较以及用于控制锁相环的振荡器的参考信号的连续转换。 每个水平同步脉冲的检测可以包括对视频信号进行采样，对采样的信号进行低通滤波，对经滤波的信号进行阈值处理，以留下具有低于阈值的电平的脉冲。 同步过程还可以包括根据对应于水平同步脉冲的参考信号的转变中心的观察窗内的残留脉冲中的，作为预定选择标准的函数来选择。

公开(公告)号：US20030053562A1

公开(公告)日：2003-03-20

申请号：US10150524

申请日：2002-05-17

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Bernard Louis-Gavet ,  Pierre-Olivier Jouffre

IPC: H03D003/00 ,  H03K009/06

CPC classification number: H04N21/6143 ,  H04L27/06 ,  H04N7/20

Abstract: The component, fully integrated onto a monolithic substrate, includes a tuner, a demodulator, and a channel decoder. The overall filtering is carried out in two parts, a baseband analog filtering and a digital Nyquist filtering removing the information of adjacent channels. It outputs a stream of MPEG data.

Abstract translation: 完全集成到单片基板上的部件包括调谐器，解调器和通道解码器。 整体滤波分为两部分：基带模拟滤波和数字奈奎斯特滤波，去除相邻信道的信息。 它输出一个MPEG数据流。

公开(公告)号：US20030038338A1

公开(公告)日：2003-02-27

申请号：US10179462

申请日：2002-06-25

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Norbert Colombet ,  Phillippe Candelier

IPC: H01L029/00

CPC classification number: H01L23/5258 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/525 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes multiple layers of integrated electronic components, and at least one electrical connection strip defining a fusible strip in one of the layers. An end of the fusible strip is connected to an integrated electronic component. An intermediate electrical connection and heat dissipation structure and a screen are disposed between the fusible strip and the integrated electronic component.

Abstract translation: 半导体器件包括多层集成电子元件，以及至少一个电连接条，其在层之一中限定可熔条。 可熔条的端部连接到集成电子部件。 中间电气连接和散热结构和屏幕设置在可熔条和集成电子部件之间。

公开(公告)号：US20030034434A1

公开(公告)日：2003-02-20

申请号：US10156710

申请日：2002-05-28

Applicant: STMICROELECTRONICS S.A.

Inventor： Laurent Simony

IPC: H01L027/00

CPC classification number: H04N5/363

Abstract: A CMOS active pixel for image sensors has a photosensitive element, a capacitive feedback element with a capacitance CF, and four transistors, namely a first transistor, two reset transistors and a transistor for the selection of the pixel. These transistors are laid out and controlled in such a way that the first transistor is mounted as an amplifier during the pixel reset phase and as a follower during the read phase.

Abstract translation: 用于图像传感器的CMOS有源像素具有光敏元件，具有电容CF的电容反馈元件和四个晶体管，即第一晶体管，两个复位晶体管和用于选择像素的晶体管。 这些晶体管被布局和控制，使得第一晶体管在像素复位阶段期间作为放大器安装，并且在读取阶段期间作为跟随器安装。

公开(公告)号：US20030022455A1

公开(公告)日：2003-01-30

申请号：US10121427

申请日：2002-04-12

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Laville ,  Serge Pontarollo

IPC: H01L021/20

CPC classification number: H01L29/66166 ,  H01L29/8605

Abstract: An integrated circuit includes an adjustment resistor, and at least one control transistor connected to a first voltage reference. An adjustment element is connected in parallel with the adjustment resistor for adjusting a combined electrical resistance of the adjustment element and the resistor. The adjustment element is connected to the control transistor, and includes a substrate, and a MOS transistor having a source, a drain, and a gate on the substrate. The MOS transistor defines a parasitic bipolar transistor with the substrate. The adjustment element further includes a first resistor connected between the substrate and the source, and a second resistor is connected between the substrate and the drain. A diode is connected in series with the second resistor between the substrate and the drain. The gate and the source of the MOS transistor are connected together with the MOS transistor being broken down so that the adjustable element forms an electrical resistance.