公开(公告)号：US20080251511A1

公开(公告)日：2008-10-16

申请号：US11733693

申请日：2007-04-10

Applicant: Myoung Jun Lee

Inventor： Myoung Jun Lee

IPC: A47C7/74

CPC classification number: H05B3/342 ,  H05B2203/003 ,  H05B2203/017 ,  H05B2203/029

Abstract: The present invention relates to an electric heating element. The electric heating element includes a core support, an inner wire wound around the core support, an intermediate dielectric layer formed around the inner wire, an outer wire wound around the intermediate dielectric layer, a connector connecting an end of the inner wire to an end of the outer wire, and an outer sheath formed around the outer wire, wherein the inner wire and outer wire are arranged to have opposite phases according to a direction of a current to attenuate magnetic fields generated from the inner wire and outer wire when a power is applied to the to inner wire and outer wire.

Abstract translation: 电加热元件技术领域本发明涉及电加热元件。 电加热元件包括芯支撑件，围绕芯支撑件缠绕的内线，围绕内线形成的中间电介质层，围绕中间电介质层缠绕的外电线，将内线的端部连接到端部的连接器 外护套形成在外线周围的外护套，其中内电线和外电线被布置为根据电流方向具有相反的相位以衰减由内电线和外线产生的磁场，当功率 应用于内线和外线。

公开(公告)号：US20080247212A1

公开(公告)日：2008-10-09

申请号：US12143126

申请日：2008-06-20

Applicant: Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

Inventor： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC: G11C5/06

CPC classification number: G11C5/063

Abstract: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

Abstract translation: 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US20080245870A1

公开(公告)日：2008-10-09

申请号：US12140960

申请日：2008-06-17

Applicant: Jae-Jun Lee ,  Young-Jun Shin

Inventor： Jae-Jun Lee ,  Young-Jun Shin

IPC: G06F17/00

CPC classification number: G06F17/30879 ,  G06K7/10722 ,  G06K19/06037 ,  G06Q20/14 ,  G06Q20/32 ,  G06Q20/322 ,  G06Q20/3276 ,  H04L29/06 ,  H04L29/12594 ,  H04L61/30 ,  H04L67/04 ,  H04L69/329 ,  H04M1/2755 ,  H04M1/72561 ,  H04M3/42 ,  H04M3/493 ,  H04M15/68 ,  H04M2215/0196 ,  H04N1/00244 ,  H04N1/00307 ,  H04N1/00326 ,  H04N1/00334 ,  H04N2201/0084 ,  H04W4/16 ,  Y10S379/91

Abstract: A method and apparatus for providing a mobile service with the use of a code pattern is disclosed In one embodiment, the method comprising: taking a photograph of a code pattern image, decoding the photographed code pattern image so as to obtain code information, extracting uniform resourse locator (URL) information corresponding to the code information, transmitting a content information request message to a service provider server corresponding to the URL information, and receiving content information corresponding to the URL information from the service provider server. According to embodiments of the present invention, it is possible to provide various and convenient mobile services to mobile terminal users using a mobile terminal, having a camera, and a code pattern containing the URL information.

Abstract translation: 公开了一种使用代码图案提供移动业务的方法和装置。在一个实施例中，该方法包括：拍摄代码图像图像，解码所拍摄的代码图形图像，以获得代码信息，提取均匀 对应于代码信息的资源定位符（URL）信息，向与URL信息相对应的服务提供者服务器发送内容信息请求消息，以及从服务提供商服务器接收与URL信息对应的内容信息。 根据本发明的实施例，可以使用具有相机的移动终端和包含URL信息的代码模式向移动终端用户提供各种和方便的移动服务。

公开(公告)号：USD577032S1

公开(公告)日：2008-09-16

申请号：US29252004

申请日：2006-01-17

Applicant: Young-Jae Ryu ,  Hyun-Chung Kim ,  Jun Lee ,  Do-Hun Im

Designer： Young-Jae Ryu ,  Hyun-Chung Kim ,  Jun Lee ,  Do-Hun Im

公开(公告)号：US20080219065A1

公开(公告)日：2008-09-11

申请号：US12123539

申请日：2008-05-20

Applicant: JAE-JUN LEE ,  HOE-JU CHUNG

Inventor： JAE-JUN LEE ,  HOE-JU CHUNG

IPC: G11C7/00

CPC classification number: H03L7/0812

Abstract: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.

Abstract translation: 用于同步半导体存储器件的延迟锁定环（DLL）电路，其可以根据外部负载的大小来控制DLL电路内的反馈回路的延迟时间，以及生成关于连接到数据的负载的信息的方法 提供同步半导体存储器件的引脚。 DLL电路包括复制输出驱动器，延迟第一延迟时间的内部时钟信号以输出第一内部时钟信号，第一延迟时间是当输出驱动器第一次加载时产生的内部时钟信号的延迟时间 第一幅度的第一延迟连接到输出驱动器的输出端，以及传输/延迟电路，当第一负载连接到输出端时，将第一延迟内部时钟信号传送到相位检测器作为第二延迟内部时钟信号， 并且通过将所述第一延迟内部时钟信号延迟第二延迟时间，将所述第二延迟内部时钟信号输出到所述相位检测器，所述第二延迟时间是由所述输出驱动器产生的内部时钟信号的延迟时间， 大于第一幅度的第二幅度连接到输出端。

公开(公告)号：US07421236B2

公开(公告)日：2008-09-02

申请号：US11483588

申请日：2006-07-11

Applicant: Jae-hyeok Jang ,  Dong-kyun Kang ,  Seung-jun Lee

Inventor： Jae-hyeok Jang ,  Dong-kyun Kang ,  Seung-jun Lee

IPC: G03G15/20

CPC classification number: G03G15/206

Abstract: A fixing unit, and an image forming apparatus having the fixing unit. The fixing unit includes a heat roller including a heat source therein, one or more pressing rollers in close contact with the heat roller, an elastic body to elastically apply pressure on both ends of the one or more pressing rollers with respect to the heat roller, a backup member to contact a central portion of the one or more pressing rollers and to apply pressure to the central portion in a longitudinal direction of the one or more pressing rollers, and a backup elastic body to elastically press the backup member towards the heat roller.

Abstract translation: 固定单元和具有定影单元的图像形成装置。 定影单元包括：加热辊，其中包括热源，一个或多个加压辊与加热辊紧密接触;弹性体，相对于加热辊在一个或多个加压辊的两端上弹性施加压力， 支撑构件，其与所述一个或多个按压辊的中心部分接触，并且在所述一个或多个按压辊的纵向方向上对所述中心部分施加压力;以及支撑弹性体，用于将所述支撑构件朝向所述加热辊 。

公开(公告)号：US07417612B2

公开(公告)日：2008-08-26

申请号：US11712337

申请日：2007-02-27

Applicant: Hyun-Su Lee ,  Byoung-Jun Lee ,  Jun-Pyo Lee ,  Young-Gil Kim ,  Hoi-Sik Moon

Inventor： Hyun-Su Lee ,  Byoung-Jun Lee ,  Jun-Pyo Lee ,  Young-Gil Kim ,  Hoi-Sik Moon

IPC: G09G3/36

CPC classification number: G09G3/2011 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3696 ,  G09G2320/0219 ,  G09G2320/0276

Abstract: A gamma voltage generator for a liquid crystal display (LCD) capable of removing residual images by compensating a gamma voltage is presented. The gamma voltage generation apparatus adjusts the common voltage by the kickback voltage for the intermediate gray level, and tunes the gamma voltages other than the intermediate gray level gamma voltage. The adjustment of the gamma voltages other than the intermediate gray level gamma voltage is achieved in such a manner that the difference between the intermediate gray level kickback voltage and the kickback voltage at one of the gray levels other than the intermediate gray level is equal to half of the difference between the sum of the two inverted gamma voltages representing the intermediate gray level gamma voltages and the sum of the two inverted gamma voltages corresponding to the selected gray level.

Abstract translation: 提出了能够通过补偿伽马电压来去除残留图像的用于液晶显示器（LCD）的伽马电压发生器。 伽马电压产生装置通过用于中间灰度级的反冲电压来调节公共电压，并调谐除了中间灰度级伽玛电压之外的伽马电压。 以中间灰度级伽玛电压以外的伽马电压的调整以这样的方式实现：中间灰度级反冲电压与中间灰度之外的灰度级之一的反冲电压之间的差等于一半 表示中间灰度级伽玛电压的两个反相伽马电压的总和与对应于所选择的灰度级的两个反相伽马电压的总和之差。

公开(公告)号：USD574840S1

公开(公告)日：2008-08-12

申请号：US29252007

申请日：2006-01-17

Applicant: Young-Jae Ryu ,  Hyun-Chung Kim ,  Jun Lee ,  Do-Hun Im

Designer： Young-Jae Ryu ,  Hyun-Chung Kim ,  Jun Lee ,  Do-Hun Im

公开(公告)号：US07405949B2

公开(公告)日：2008-07-29

申请号：US11603648

申请日：2006-11-22

Applicant: Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

Inventor： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC: H05K7/14

CPC classification number: G11C5/063

Abstract: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

Abstract translation: 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US20080176370A1

公开(公告)日：2008-07-24

申请号：US12002241

申请日：2007-12-13

Applicant: Choul Joo Ko ,  Yong Jun Lee

Inventor： Choul Joo Ko ,  Yong Jun Lee

IPC: H01L21/76

CPC classification number: H01L27/0629 ,  H01L28/40

Abstract: In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

Abstract translation: 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，在器件隔离层上形成底部电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域中形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。