中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

308 records (took 0.025 seconds)

    Memory cell with floating gate, coupling gate and erase gate, and method of making same
    281.
    发明授权
    Memory cell with floating gate, coupling gate and erase gate, and method of making same 有权

    公开(公告)号：US10998325B2

    公开(公告)日：2021-05-04

    申请号：US16208297

    申请日：2018-12-03

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Catherine Decobert ,  Hieu Van Tran ,  Nhan Do

    IPC: G11C16/16 ,  H01L27/11521 ,  G11C16/26 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

    Abstract: A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.

    Neural network classifier using array of two-gate non-volatile memory cells
    285.
    发明授权
    Neural network classifier using array of two-gate non-volatile memory cells 有权

    公开(公告)号：US10699779B2

    公开(公告)日：2020-06-30

    申请号：US16382013

    申请日：2019-04-11

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G11C16/04 ,  G11C11/54 ,  G06N3/04 ,  H01L29/423 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/10

    Abstract: A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

    Split-gate flash memory array with byte erase operation
    288.
    发明授权
    Split-gate flash memory array with byte erase operation 有权

    公开(公告)号：US10607703B2

    公开(公告)日：2020-03-31

    申请号：US16042000

    申请日：2018-07-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11521

    Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

Patent Agency Ranking