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公开(公告)号：US06760240B2
公开(公告)日：2004-07-06
申请号：US10065822
申请日：2002-11-22
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macro's are inverted with respect to adjacent macros to balance parasitic capacitances across the array.
摘要翻译： 公开了一种用于内容可寻址存储器（CAM）单元阵列的方法和结构。 每个CAM单元具有搜索线和平行于搜索线的位线。 跨阵列，CAM单元的搜索行和位线是交叉的，以便搜索行和位线在数组之间交替。 CAM单元宏相对于相邻的宏反转，以平衡阵列上的寄生电容。
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公开(公告)号：US06487101B1
公开(公告)日：2002-11-26
申请号：US09968814
申请日：2001-10-02
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/043
摘要： A method and structure for a content addressable memory (CAM) array having a plurality of memory cells. Each of the memory cells has capacitive storage devices, transistors connected to the storage devices, a wordline connected to and controlling the transistors, bitlines connected to the storage devices through the transistors, combined search and global bitlines connected to the capacitive storage devices. These cells are further arranged into columns, each containing multiplexers connected to the combined search and global bitlines, data-in lines connected to the multiplexers, and search-data lines connected to the multiplexers. Further, the multiplexers select between the data-in lines and the search-data lines to allow the combined search and global bitlines to be alternatively used as data lines and search lines. Also, in the invention each of the columns further has drivers between the multiplexers and the combined search and global bitlines. The drivers drive signals between the multiplexers and the combined search and global bitlines during search and write operations.
摘要翻译： 一种具有多个存储单元的内容可寻址存储器（CAM）阵列的方法和结构。 每个存储单元具有电容存储器件，连接到存储器件的晶体管，连接到晶体管和控制晶体管的字线，通过晶体管连接到存储器件的位线，连接到电容存储器件的组合搜索和全局位线。 这些单元进一步排列成列，每列包含连接到组合搜索和全局位线的多路复用器，连接到多路复用器的数据输入线以及连接到多路复用器的搜索数据线。 此外，多路复用器在数据输入行和搜索数据行之间进行选择以允许将组合搜索和全局位线替代地用作数据线和搜索行。 此外，在本发明中，每个列还具有多路复用器和组合的搜索和全局位线之间的驱动器。 在搜索和写入操作期间，驱动器在多路复用器之间驱动信号和组合的搜索和全局位线。
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公开(公告)号：US06252443B1
公开(公告)日：2001-06-26
申请号：US09295157
申请日：1999-04-20
申请人： Jean-Marc Dortu , Albert M. Chu , Frank Ferraiolo
发明人： Jean-Marc Dortu , Albert M. Chu , Frank Ferraiolo
IPC分类号： H03L706
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0814
摘要： A delay locked loop circuit, in accordance with the invention, includes a delay line for providing a delay through the delay line in accordance with a control signal, the delay line being connected across an input node and an output node. A delay element is connected to the input node, the delay element for providing a predetermined delay value to an input signal from the input node to provide a delayed input signal. A phase comparator is connected to the output node and the delay element for comparing phase differences between an output signal and the delayed input signal and for outputting the control signal to the delay line such that the delay line provides the predetermined delay value to the delay line across the input and output nodes.
摘要翻译： 根据本发明的延迟锁定环路电路包括延迟线，用于根据控制信号通过延迟线提供延迟，延迟线跨输入节点和输出节点连接。 延迟元件连接到输入节点，延迟元件用于向来自输入节点的输入信号提供预定的延迟值，以提供延迟的输入信号。 相位比较器连接到输出节点和延迟元件，用于比较输出信号和延迟输入信号之间的相位差，并将控制信号输出到延迟线，使得延迟线向延迟线提供预定的延迟值 跨输入和输出节点。
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公开(公告)号：US09052356B2
公开(公告)日：2015-06-09
申请号：US13396775
申请日：2012-02-15
IPC分类号： G01R31/00 , G01R31/311
CPC分类号： G01R31/311
摘要： A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.
摘要翻译： 半导体器件结构嵌入半导体芯片内，通过运行多个已知电流通过器件来校准光子发射光度标度。 该方法包括将至少一个光子发射装置嵌入到具有至少一个功能装置的集成电路中。 控制电流被施加到至少一个光子发射装置。 捕获由至少一个光子发射装置产生的光子发射强度。 计算出至少一个光子发射装置的电流密度。 测试电流被施加到所述至少一个功能装置。 捕获由至少一个功能装置产生的光子发射强度。 基于与计算出的至少一个光子发射装置的电流密度的比较来估计至少一个功能装置的电流密度。
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25.发明授权公开(公告)号：US08726210B2
公开(公告)日：2014-05-13
申请号：US13416015
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element.
摘要翻译： 提供系统和方法以通过调节系统过程变化来优化关键路径，例如IC设计中的区域时序变化。 一种方法包括在关键路径内确定半导体芯片设计中的元件的物理位置。 该方法还包括基于与元件相关联的多晶硅导体周长密度来调制半导体芯片设计的系统过程变化以加速关键路径。
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公开(公告)号：US08576526B2
公开(公告)日：2013-11-05
申请号：US13398038
申请日：2012-02-16
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device with reduced current leakage, and a related method. In one embodiment, an ESD protection device for an integrated circuit (IC) is provided. The ESD protection device includes: a resistor-capacitor (RC) timing circuit for selectively turning on the ESD protection device during an ESD event; a trigger circuit for receiving an output of the RC timing circuit and generating a trigger pulse for driving at least one of: a first ESD clamp and a second ESD clamp; and a selection circuit for selecting one of: the trigger circuit or a charge pump for controlling the second ESD clamp.
摘要翻译： 本发明的一个方面提供一种具有降低的电流泄漏的静电放电（ESD）保护装置及相关方法。 在一个实施例中，提供了一种用于集成电路（IC）的ESD保护装置。 ESD保护装置包括：电阻 - 电容（RC）定时电路，用于在ESD事件期间选择性地接通ESD保护装置; 触发电路，用于接收RC定时电路的输出并产生用于驱动下列至少一个的触发脉冲：第一ESD钳位和第二ESD钳位; 以及用于选择触发电路或用于控制第二ESD钳位的电荷泵之一的选择电路。
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公开(公告)号：US20130275821A1
公开(公告)日：2013-10-17
申请号：US13445187
申请日：2012-04-12
申请人： George M. BRACERAS , Albert M. CHU , Kevin W. Gorman , Michael R. OUELLETTE , Ronald A. PIRO , Daryl M. SEITZER , Rohit SHETTY , Thomas W. WYCKOFF
发明人： George M. BRACERAS , Albert M. CHU , Kevin W. Gorman , Michael R. OUELLETTE , Ronald A. PIRO , Daryl M. SEITZER , Rohit SHETTY , Thomas W. WYCKOFF
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译： 提供了具有冗余性和使用方法的只读存储器（ROM）。 具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。 一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。 字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。 提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。 提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。
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公开(公告)号：US20130215539A1
公开(公告)日：2013-08-22
申请号：US13398038
申请日：2012-02-16
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device with reduced current leakage, and a related method. In one embodiment, an ESD protection device for an integrated circuit (IC) is provided. The ESD protection device includes: a resistor-capacitor (RC) timing circuit for selectively turning on the ESD protection device during an ESD event; a trigger circuit for receiving an output of the RC timing circuit and generating a trigger pulse for driving at least one of: a first ESD clamp and a second ESD clamp; and a selection circuit for selecting one of: the trigger circuit or a charge pump for controlling the second ESD clamp.
摘要翻译： 本发明的一个方面提供一种具有降低的电流泄漏的静电放电（ESD）保护装置及相关方法。 在一个实施例中，提供了一种用于集成电路（IC）的ESD保护装置。 ESD保护装置包括：电阻 - 电容（RC）定时电路，用于在ESD事件期间选择性地接通ESD保护装置; 触发电路，用于接收RC定时电路的输出并产生用于驱动下列至少一个的触发脉冲：第一ESD钳位和第二ESD钳位; 以及用于选择触发电路或用于控制第二ESD钳位的电荷泵之一的选择电路。
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29.发明授权Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal 有权集成电路中的电压检测电路和产生触发标志信号的方法公开(公告)号：US07847605B2
公开(公告)日：2010-12-07
申请号：US12242114
申请日：2008-09-30
IPC分类号： H03L7/00
CPC分类号： H03K5/153
摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译： 一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。
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公开(公告)号：US07818694B2
公开(公告)日：2010-10-19
申请号：US12342353
申请日：2008-12-23
申请人： Robert J Allen , Faye D Baker , Albert M Chu , Michael S Gray , Jason Hibbeler , Daniel N Maynard , Mervyn Y Tan , Robert F Walker
发明人： Robert J Allen , Faye D Baker , Albert M Chu , Michael S Gray , Jason Hibbeler , Daniel N Maynard , Mervyn Y Tan , Robert F Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译： 使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。 该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。
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