公开(公告)号：US20110107059A1

公开(公告)日：2011-05-05

申请号：US12916833

申请日：2010-11-01

Applicant: Sang Yoon OH ,  Bhum-Cheol LEE ,  Jung-Hee LEE ,  Dong-Myoung BAEK ,  Seung-Woo LEE

Inventor： Sang Yoon OH ,  Bhum-Cheol LEE ,  Jung-Hee LEE ,  Dong-Myoung BAEK ,  Seung-Woo LEE

IPC: G06F15/80 ,  G06F9/02

CPC classification number: G06F9/5027

Abstract: A multilayer parallel processing apparatus. The multilayer parallel processing apparatus includes two or more hierarchical parallel processing units, each configured to process flow data corresponding to a hierarchy that is allocated thereto in response to inputting pieces of flow data configured with two or more hierarchies, and a common database configured to be accessed by the two or more hierarchical parallel processing units and store processing results of each of the hierarchical parallel processing units.

Abstract translation: 多层并行处理装置。 多层并行处理装置包括两个或多个分层并行处理单元，每个分层并行处理单元被配置为响应于输入配置有两个或更多个层次的流数据而处理与分配给其的层次相对应的流数据，以及配置为 由两个或多个分级并行处理单元访问，并存储每个分级并行处理单元的处理结果。

公开(公告)号：US20110072440A1

公开(公告)日：2011-03-24

申请号：US12821127

申请日：2010-06-22

Applicant: Jung Hee LEE ,  Sang Yoon OH ,  Dong Myoung BAEK ,  Bhum Cheol LEE

Inventor： Jung Hee LEE ,  Sang Yoon OH ,  Dong Myoung BAEK ,  Bhum Cheol LEE

IPC: G06F9/46

CPC classification number: G06F9/5083

Abstract: A parallel processing system determines whether to drive all or some processors so as to process data that are input based on capacity or time for processing the input data. Also, the system temporarily stores the data that are processed and output by the respective processors, and controls the same to be output when it becomes the calculated output time based on the traffic processing time for the input data.

Abstract translation: 并行处理系统确定是驱动全部处理器还是某些处理器，以处理基于输入数据的容量或时间输入的数据。 此外，系统临时存储由各个处理器处理和输出的数据，并且当其基于用于输入数据的业务处理时间变为计算的输出时间时将其控制为输出。

公开(公告)号：US20110016232A1

公开(公告)日：2011-01-20

申请号：US12828622

申请日：2010-07-01

Applicant: Seung-Woo LEE ,  Bhum-Cheol LEE ,  Seung-Hwan KIM ,  Woo-Young CHOI ,  Tae-Whan YOO

Inventor： Seung-Woo LEE ,  Bhum-Cheol LEE ,  Seung-Hwan KIM ,  Woo-Young CHOI ,  Tae-Whan YOO

IPC: G06F15/16

CPC classification number: H04J3/0685 ,  H04L7/04 ,  H04L69/28 ,  H04L69/323

Abstract: A time stamping apparatus and method for network timing synchronization are provided. A receiving apparatus receives data from a transmitting apparatus, generates a synchronization pulse signal synchronized with a local clock of the transmitting apparatus based on the received data, wherein the received data include information regarding the transmission time of the data, measured using the local clock of the transmitting apparatus, and the receiving apparatus measures the reception time of the data using the synchronization pulse signal. Therefore, accurate network timing synchronization may be achieved.

Abstract translation: 提供了一种用于网络定时同步的时间戳装置和方法。 接收装置从发送装置接收数据，基于接收到的数据生成与发送装置的本地时钟同步的同步脉冲信号，其中，所接收的数据包括关于使用本地时钟测量的数据的发送时间的信息 发送装置和接收装置使用同步脉冲信号来测量数据的接收时间。 因此，可以实现精确的网络定时同步。

公开(公告)号：US20100086091A1

公开(公告)日：2010-04-08

申请号：US12575375

申请日：2009-10-07

Applicant: Dae Geun Park ,  Jung Hee Lee ,  Seung Woo Lee ,  Bhum Cheol Lee

Inventor： Dae Geun Park ,  Jung Hee Lee ,  Seung Woo Lee ,  Bhum Cheol Lee

IPC: H04L7/00

CPC classification number: G04R20/18 ,  H04J3/0667 ,  H04L69/28

Abstract: Provided is a method and apparatus for synchronizing a time of day (TOD) in a convergent network, wherein the TOD is received from a time server connected in the convergent network and is provided to a terminal connected in a wired or wireless network, specifically a terminal connected in a heterogeneous network, that requires TOD information. The apparatus includes a time server that provides standard TOD information, a gateway or a host personal computer (PC) that provides the standard TOD information of the time server to the terminal in a 3rd layer or lower instead of an upper layer of the open system interconnection (OSI) 7 layer model, and the terminal that adjusts a local clock according to the provided standard TOD information. According to the method and apparatus, the terminal not only maintains a very precise TOD by obtaining TOD information of the time server periodically or when required, but also obtains the TOD information without using application software for processing the TOD information. Accordingly, power consumption of the terminal is decreased.

Abstract translation: 提供了一种用于在收敛网络中同步时间（TOD）的方法和装置，其中，从连接在会聚网络中的时间服务器接收TOD并将其提供给连接在有线或无线网络中的终端，具体地， 终端连接在异构网络中，需要TOD信息。 该装置包括提供标准TOD信息的时间服务器，网关或主机个人计算机（PC），其提供时间服务器的标准TOD信息到第三层或更低层的终端，而不是开放系统的上层 互连（OSI）7层模型，以及根据提供的标准TOD信息调整本地时钟的终端。 根据该方法和装置，终端不仅通过周期性地或者需要时间地获取时间服务器的TOD信息，而且在不使用用于处理TOD信息的应用软件的情况下获取TOD信息，来维持非常精确的TOD。 因此，终端的功耗降低。

公开(公告)号：US20100040090A1

公开(公告)日：2010-02-18

申请号：US12389944

申请日：2009-02-20

Applicant: Seung Woo LEE ,  Hyun Yong HWANG ,  Dae Geun PARK ,  Bhum cheol LEE

Inventor： Seung Woo LEE ,  Hyun Yong HWANG ,  Dae Geun PARK ,  Bhum cheol LEE

IPC: H04J3/06

CPC classification number: H04J3/0673 ,  H04J3/0664

Abstract: Provided are a time synchronization method allowing a fixed time delay and a bridge that is interposed between a master and a slave, according to the method. In the bridge, a predetermined time after the synchronization packet is set as an output time of the synchronization packet and the synchronization packet is output at the output time. Accordingly, it is possible to delay synchronization packets in the bridge for the same time, thereby increasing the time synchronization precision.

Abstract translation: 提供了一种允许固定时间延迟的时间同步方法，以及插入在主机和从机之间的桥接器。 在桥中，将同步分组之后的预定时间设置为同步分组的输出时间，并且在输出时输出同步分组。 因此，可以同时延迟桥中的同步分组，从而增加时间同步精度。

公开(公告)号：US06904047B2

公开(公告)日：2005-06-07

申请号：US09860273

申请日：2001-05-17

Applicant: Man-Soo Han ,  Jung-Hee Lee ,  In-Tack Han ,  Bhum-Cheol Lee

Inventor： Man-Soo Han ,  Jung-Hee Lee ,  In-Tack Han ,  Bhum-Cheol Lee

IPC: H04L12/70 ,  H04L12/933 ,  H04L12/935 ,  H04L12/56

CPC classification number: H04L49/1576 ,  H04L49/1523 ,  H04L49/3018 ,  H04L49/3027 ,  H04L2012/5679 ,  H04L2012/5683

Abstract: A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method. The SIM method consists of three operations, those are, request operation, grant operation, and accepting operation, and in the SIM method, the operations are iteratively carried out several times in one cell period, thereby matching efficiency can be increased. Each input buffered module determines simultaneously multiple FIFO queues served in one cell period, so that the SIM method with multiple selection ability has higher speed operations and better performance than conventional scheduling methods.

Abstract translation: 提供一种用于调度输入和输出缓冲的ATM或分组交换机的方法，更具体地说，涉及一种适用于高速大型交换机的输入和输出缓冲交换机的小区调度方法。 输入和输出缓冲开关具有多个开关平面，其结构用于补偿由输入缓冲开关的HOL（线头）阻塞导致的输入缓冲开关的性能下降。 输入和输出缓冲交换机由输入缓冲区模块组成，分组几个输入端口和输出端口以及输出缓冲模块，每个输入缓冲区模块都有相应的模块输出缓冲模块的多个FIFO队列。 在具有多个交换平面的输入和输出缓冲交换机中，使用简单的迭代匹配（SIM）方法进行小区调度。 SIM方法由三种操作，即请求操作，授权操作和接受操作三种操作，在SIM方法中，在一个单元周期内对该操作进行多次迭代，可以提高匹配效率。 每个输入缓冲模块同时确定在一个单元周期内服务的多个FIFO队列，使得具有多种选择能力的SIM方法具有比传统调度方法更高的速度操作和更好的性能。

公开(公告)号：US06633568B1

公开(公告)日：2003-10-14

申请号：US09494729

申请日：2000-01-31

Applicant: Man Soo Han ,  Jung Hee Lee ,  Gab Joong Jeong ,  Bhum Cheol Lee

Inventor： Man Soo Han ,  Jung Hee Lee ,  Gab Joong Jeong ,  Bhum Cheol Lee

IPC: H04L1254

CPC classification number: H04L49/153 ,  H04L12/5601 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/254 ,  H04L49/255 ,  H04L49/30 ,  H04L49/3081 ,  H04L2012/5679 ,  H04L2012/5683

Abstract: A two-dimensional round-robin scheduling method with multiple selection is provided. The two-dimensional round-robin scheduling method in accordance with an embodiment of the present invention includes following steps. First step is for checking whether a request is received from the input buffer module and building mxm request matrix r(i,j), i,j=1, . . . , m. Second step is for setting mxm search pattern matrix, d(i,j), i,j=1, . . . , m. The search pattern matrix describes search sequence, S=1, . . . , m. Third step is for initializing elements of mxm allocation matrix a(i,j), i,j=1, . . . , m. The allocation matrix contains information whether transmission request is accepted and which switching plane the accepted request uses in transmission. Fourth step is for examining a request matrix in accordance with the search sequence S and finding r(i,j) that sent a request. Fifth step is for setting a(i,j) for all (i,j) pairs found in the fourth step so that elements of allocation matrix at ith row have different values in range from 1 to n and elements of allocation matrix at jth column have different values in range from 1 to n. Sixth step is for repeating the fourth step and the fifth step as the search sequence S is increased from 1 to m by 1.

Abstract translation: 提供了一种具有多重选择的二维轮询调度方法。 根据本发明的实施例的二维轮询调度方法包括以下步骤。 第一步是检查是否从输入缓冲区模块接收请求，并建立mxm请求矩阵r（i，j），i，j = 1， 。 。 ，m。 第二步是设置mxm搜索模式矩阵，d（i，j），i，j = 1，。 。 。 ，m。 搜索模式矩阵描述了搜索序列S = 1。 。 。 ，m。 第三步是初始化mxm分配矩阵a（i，j），i，j = 1，...的元素。 。 。 ，m。 分配矩阵包含传输请求是否被接受以及接受请求在传输中使用的切换平面的信息。 第四步是根据搜索序列S检查请求矩阵，并找到发送请求的r（i，j）。 第五步是为了在第四步中发现的所有（i，j）对设置一个（i，j），使得第i行的分配矩阵的元素在1到n的范围内具有不同的值，并且第j列的分配矩阵的元素 在1到n的范围内具有不同的值。 第六步是当搜索序列S从1增加到1时重复第四步和第五步骤。

公开(公告)号：US06346895B1

公开(公告)日：2002-02-12

申请号：US09769099

申请日：2001-01-24

Applicant: Bhum-Cheol Lee ,  Jong-Moo Sohn ,  Eun-Chang Choi ,  Kwon-Chul Park

Inventor： Bhum-Cheol Lee ,  Jong-Moo Sohn ,  Eun-Chang Choi ,  Kwon-Chul Park

IPC: H03M500

CPC classification number: H03M5/00

Abstract: A method for using a nibble(partial bits of word) inversion code in a network system includes the steps of: a) adding 1 redundancy bit to n bit source data and generating a pre-code, n being an even number of 2 or over; b) deciding the number of transitions in the generated pre-code; c) determining the pre-code as a code word if the number of transitions in the pre-code is greater than or equal to 1+n/2 in a deciding result; d) inverting alternate bits including the redundancy bit among bits constructing the pre-code and generating the code word, if the number of transitions in the pre-code is less than n/2 in the deciding result; e) determining the pre-code as the code word in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is not an in-band signaling and not a special word in the deciding result; and f) inverting the nibble among the bits constructing the pre-code and generating the code word, in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is an in-band signaling or is a special word in the deciding result.

Abstract translation: 一种在网络系统中使用半字节（部分位字）反转码的方法包括以下步骤：a）将1个冗余比特加到n比特源数据并产生一个预编码，n是2或更多的偶数 ; b）决定生成的代码中的转换次数; c）如果所述预代码中的转换次数在决定结果中大于或等于1 + n / 2，则将所述预代码确定为代码字; d）如果所述预代码中的转换次数小于所述判定结果中的n / 2，则将包括构成所述预代码的位中的所述冗余位的交替位反转并生成所述代码字; e）在预编码中的转换次数等于n / 2并且同时源数据不是带内信令而不是决定结果中的特殊字的情况下，将前缀代码确定为码字 ; 以及f）在构成前代码的比特中产生半字节并产生码字，在预编码中的转换次数等于n / 2的情况下，并且源数据是带内信令或 是决定结果中的一个特殊字。

公开(公告)号：US5675293A

公开(公告)日：1997-10-07

申请号：US582882

申请日：1996-01-04

Applicant: Bhum Cheol Lee ,  Jae Young Kim ,  Eun Chang Choi ,  Kwon Chul Park

Inventor： Bhum Cheol Lee ,  Jae Young Kim ,  Eun Chang Choi ,  Kwon Chul Park

IPC: H03K3/35 ,  H03K3/03 ,  H03B5/02

CPC classification number: H03K3/0315 ,  Y10S331/03

Abstract: A voltage controlled ring oscillator having a reduced voltage controlled oscillator (VCO) gain by controlling only the fall time of the period of the VCO using integrated circuits and logic circuits. The VCO includes a mixer/inverter circuit, a logic circuit, a delay/inverter circuit, a first delay circuit, a second delay circuit, and a third delay circuit. The VCO gain is reduced by controlling only one pulse width of the logic level High and one pulse width of the logic level Low of the oscillating period. Furthermore, the VCO can be logically controlled by using a simple logic circuit as a component of the VCO.

Abstract translation: 通过仅使用集成电路和逻辑电路仅控制VCO的周期的下降时间，具有降压控制振荡器（VCO）增益的压控环形振荡器。 VCO包括混频器/反相器电路，逻辑电路，延迟/反相器电路，第一延迟电路，第二延迟电路和第三延迟电路。 通过仅控制逻辑电平高的一个脉冲宽度和振荡周期的逻辑电平低的一个脉冲宽度来减小VCO增益。 此外，可以通过使用简单的逻辑电路作为VCO的组件来逻辑地控制VCO。

公开(公告)号：US08743883B2

公开(公告)日：2014-06-03

申请号：US12843166

申请日：2010-07-26

Applicant: Jung Hee Lee ,  Jung Sik Kim ,  Young Ho Park ,  Bhum Cheol Lee

Inventor： Jung Hee Lee ,  Jung Sik Kim ,  Young Ho Park ,  Bhum Cheol Lee

IPC: H04J1/02 ,  H04L12/56

CPC classification number: H04L47/10 ,  G06F1/3203 ,  G06F9/5038 ,  G06F2209/506

Abstract: Provided is a data flow parallel processing apparatus and method. The data flow parallel processing apparatus may include a flow discriminating unit to discriminate a flow of input first data, a processor allocating unit to allocate, to the first data, a processor that is not operating among a plurality of processors, a sequence determining unit to determine a sequence number of the first data when a second data having the same flow as the discriminated flow is being processed by any one processor composing the plurality of processors, and an alignment unit to receive the first data processed by the allocated processor and to output the received first data based on the determined sequence number.

Abstract translation: 提供了一种数据流并行处理装置和方法。 数据流并行处理装置可以包括：流鉴定单元，用于识别输入的第一数据的流;处理器分配单元，用于向第一数据分配不在多个处理器之间运行的处理器;序列确定单元， 当由构成所述多个处理器的任何一个处理器处理具有与所识别的流相同的流的第二数据时，确定第一数据的序列号;以及对准单元，用于接收由所分配的处理器处理的第一数据并输出 基于确定的序列号接收的第一数据。