公开(公告)号：US06866416B1

公开(公告)日：2005-03-15

申请号：US10635996

申请日：2003-08-07

Applicant: Mehrdad Mahanpour ,  Alice H. Choi ,  Mohammad Massoodi ,  Boon-Yong Ang

Inventor： Mehrdad Mahanpour ,  Alice H. Choi ,  Mohammad Massoodi ,  Boon-Yong Ang

IPC: G01N25/72 ,  G01N33/00 ,  G01N25/00

CPC classification number: G01N25/72 ,  G01N2033/0095

Abstract: A method and semiconductor device for detecting a heat generating failure in an unpassivated semiconductor device. The semiconductor device has an unpassivated surface and a heat generating failure, e.g., short circuit. A coating may be applied to the unpassivated surface of the semiconductor device. The coating may be non-electrically conducting and capable of localizing heat generated by the failure in a particular area. The semiconductor device may be biased. The failure may then be detected by detecting a location of the heat generated by the failure in the coating.

Abstract translation: 一种用于检测未通过半导体器件的发热故障的方法和半导体器件。 半导体器件具有未钝化的表面和发热故障，例如短路。 可以将涂层施加到半导体器件的未钝化表面。 涂层可以是非导电的并且能够定位由特定区域中的故障产生的热量。 半导体器件可能被偏置。 然后可以通过检测由涂层中的故障产生的热的位置来检测故障。

公开(公告)号：US06824446B1

公开(公告)日：2004-11-30

申请号：US09974241

申请日：2001-10-10

Applicant: Boon Yong Ang ,  Kenneth R. Harris

Inventor： Boon Yong Ang ,  Kenneth R. Harris

IPC: B24B100

CPC classification number: B24B37/11 ,  B24B9/065 ,  B24B37/013 ,  B24B49/12

Abstract: An outer edge ring of a semiconductor wafer is polished to prevent delamination and peeling-off of at least one layer of material deposited near the outer edge of the semiconductor wafer during fabrication of integrated circuits. The semiconductor wafer is mounted on a wafer chuck, and the wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semiconductor wafer as the semiconductor wafer is rotating. The polishing pad has a polishing surface that faces and contacts the outer edge ring of the semiconductor wafer as the polishing pad is moved toward the semiconductor wafer to polish the outer edge ring of the semiconductor wafer. The outer edge ring has the at least one layer of material that is polished off by the polishing surface of the polishing pad. The polishing surface of the polishing pad may be tapered such that the edge of an upper layer of material that is disposed further from the semiconductor wafer is disposed more inward toward the center of the semiconductor wafer such that the upper layer of material is not likely to delaminate and peel-off away from a lower abutting layer of material on the semiconductor wafer. Furthermore, a photodetector may determine sufficient polishing of the outer edge ring of the semiconductor wafer.

Abstract translation: 抛光半导体晶片的外边缘环，以防止在集成电路的制造期间沉积在半导体晶片的外边缘附近的至少一层材料的分层和剥离。 将半导体晶片安装在晶片卡盘上，并且保持半导体晶片的晶片卡盘旋转，使得半导体晶片旋转。 当半导体晶片旋转时，抛光垫朝向半导体晶片移动。 当抛光垫向半导体晶片移动以抛光半导体晶片的外边缘环时，抛光垫具有面向并接触半导体晶片的外边缘环的抛光表面。 外边缘环具有由抛光垫的抛光表面抛光的至少一层材料。 抛光垫的抛光表面可以是锥形的，使得更远离半导体晶片的材料的上层的边缘更靠近半导体晶片的中心设置，使得上层材料不可能 从半导体晶片上的下部邻接材料层剥离和剥离。 此外，光电检测器可以确定半导体晶片的外边缘环的充分抛光。

公开(公告)号：US06589860B1

公开(公告)日：2003-07-08

申请号：US09811190

申请日：2001-03-16

Applicant: Boon Yong Ang ,  Kenneth Roy Harris ,  Samantha Lee

Inventor： Boon Yong Ang ,  Kenneth Roy Harris ,  Samantha Lee

IPC: H01L2144

CPC classification number: H01L22/34 ,  G01R31/307 ,  G01R35/005 ,  H01L21/76892

Abstract: A system and method for calibrating/characterizing an electron beam (e-beam) defect inspection tool for detecting voltage contrast defects includes deliberately forming defects in a test portion of a semiconductor wafer by deliberately forming an open, short, or abnormal resistance in a circuit feature. The test portion can be in the scribe lines of a product die or on a fully populated test wafer, so that the calibration of the e-beam tool for certain inspection layers of a fabrication technology can be determined. The electron microscope output of the is checked against the known defects to determine whether the tool is accurately sensing defects.

Abstract translation: 用于校准/表征用于检测电压对比度缺陷的电子束（电子束）缺陷检查工具的系统和方法包括通过在电路中故意形成开路，短路或异常电阻来故意形成半导体晶片的测试部分中的缺陷 特征。 测试部分可以在产品模具的划线或完全填充的测试晶片上，使得可以确定用于制造技术的某些检查层的电子束工具的校准。 根据已知缺陷检查电子显微镜输出，以确定工具是否精确地感测到缺陷。

公开(公告)号：US07312625B1

公开(公告)日：2007-12-25

申请号：US11449197

申请日：2006-06-08

Applicant: Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

Inventor： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

IPC: G01R31/00

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  G01R31/2858

Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

Abstract translation: 描述了用于制造用于超大规模集成（“VLSI”）处理的晶体管的测试电路及其使用方法。 晶体管形成阵列。 第一解码器耦合到晶体管的栅极并被配置为选择性地将电压传递到栅极。 第二解码器耦合到晶体管的漏极区域并且被配置为选择性地将电压传递到晶体管的漏极区域。 第三解码器耦合到晶体管的源极区域并且被配置为选择性地将电压传递到晶体管的源极区域。 第四解码器耦合到晶体管的体区，并且被配置为选择性地将电压传递到晶体管的体区。

公开(公告)号：US07242102B2

公开(公告)日：2007-07-10

申请号：US10887585

申请日：2004-07-08

Applicant: Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon S Chan ,  Cinti X Chen

Inventor： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon S Chan ,  Cinti X Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042

Abstract: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Abstract translation: 根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。 该结构还包括位于金属焊盘上的层间电介质层。 该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。 端子通孔仅沿着金属焊盘的一侧延伸。 该结构还包括位于层间电介质层和端子通孔中的端子金属层。 所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。 层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。