公开(公告)号：US07923811B1

公开(公告)日：2011-04-12

申请号：US12043910

申请日：2008-03-06

申请人： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

发明人： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.

摘要翻译： 电子熔丝（“E-fuse”）单元形成在半导体衬底上。 电子熔断器单元具有熔丝元件，熔丝链从第一熔丝端子穿过厚电介质结构延伸到第二熔丝端子。 第一和第二熔丝端子通过薄的电介质层与半导体衬底分离。

公开(公告)号：US20080101146A1

公开(公告)日：2008-05-01

申请号：US11588775

申请日：2006-10-27

申请人： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

发明人： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

IPC分类号： G11C17/18

CPC分类号： G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

摘要翻译： 具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。 耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。 在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

公开(公告)号：US07301194B1

公开(公告)日：2007-11-27

申请号：US10990066

申请日：2004-11-15

申请人： Sunhom Paak ,  David Kuan-Yu Liu ,  Anders T. Dejenfelt ,  Cyrus Chang ,  Qi Lin ,  Phillip A. Young

发明人： Sunhom Paak ,  David Kuan-Yu Liu ,  Anders T. Dejenfelt ,  Cyrus Chang ,  Qi Lin ,  Phillip A. Young

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/11521

摘要： A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configuration allows for an area-efficient layout that is easily shrinkable as compared to prior art memory cells. In addition, stacking the control and floating gates results in higher capacitive coupling. The EEPROM cell also includes an access gate, a tunnel capacitor, and at least one inverter. In some embodiments, the EEPROM cell can be advantageously used to configure programmable logic without need for a conloading step.

摘要翻译： 具有双重多重布置的非易失性EEPROM单元提供存储的数据而无需读出放大器，从而降低功率需求。 EEPROM单元在第一多晶硅层中具有浮置栅极，并且控制栅极与第二多晶硅层中的浮置栅极重叠。 与现有技术的存储单元相比，该配置允许容易收缩的面积效率的布局。 此外，堆叠控制和浮动栅极导致更高的电容耦合。 EEPROM单元还包括存取栅极，隧道电容器和至少一个反相器。 在一些实施例中，EEPROM单元可有利地用于配置可编程逻辑，而不需要进行加载步骤。

公开(公告)号：US07280421B2

公开(公告)日：2007-10-09

申请号：US11483007

申请日：2006-07-06

申请人： Phillip A. Young ,  Sunhom Paak

发明人： Phillip A. Young ,  Sunhom Paak

IPC分类号： G11C7/00

CPC分类号： H03K19/17748 ,  G01R31/318516 ,  G11C11/41 ,  G11C14/00 ,  G11C2029/3202 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/1778

摘要： A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated control signal. When the control signal is de-activated, the latch is de-coupled from the first voltage supply terminal and coupled to the non-volatile memory cell. If the non-volatile memory cell is programmed, the latch is coupled to a second voltage supply terminal, thereby storing a second logic value in the latch. If the non-volatile memory cell is erased, the latch is isolated from the second voltage supply terminal, and the first logic value remains stored in the latch. The latch can also be directly written through one or more access transistors, thereby facilitating testing.

摘要翻译： 配置电路包括锁存器和专用非易失性存储器单元。 最初编程或擦除非易失性存储单元。 然后，锁存器被设置为通过响应于激活的控制信号将锁存器耦合到第一电压供应端子来存储第一逻辑值。 当控制信号被去激活时，锁存器从第一电压提供端被去耦合并耦合到非易失性存储单元。 如果非易失性存储单元被编程，则锁存器耦合到第二电压供应端，从而在锁存器中存储第二逻辑值。 如果非易失性存储单元被擦除，则锁存器与第二电压源端子隔离，并且第一逻辑值保持存储在锁存器中。 锁存器也可以通过一个或多个存取晶体管直接写入，从而便于测试。

公开(公告)号：US07092293B1

公开(公告)日：2006-08-15

申请号：US10721855

申请日：2003-11-25

申请人： Phillip A. Young ,  Sunhom Paak

发明人： Phillip A. Young ,  Sunhom Paak

IPC分类号： G11C11/34

CPC分类号： H03K19/17748 ,  G01R31/318516 ,  G11C11/41 ,  G11C14/00 ,  G11C2029/3202 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/1778

摘要： A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated control signal. When the control signal is de-activated, the latch is de-coupled from the first voltage supply terminal and coupled to the non-volatile memory cell. If the non-volatile memory cell is programmed, the latch is coupled to a second voltage supply terminal, thereby storing a second logic value in the latch. If the non-volatile memory cell is erased, the latch is isolated from the second voltage supply terminal, and the first logic value remains stored in the latch. The latch can also be directly written through one or more access transistors, thereby facilitating testing.

摘要翻译： 配置电路包括锁存器和专用非易失性存储器单元。 最初编程或擦除非易失性存储单元。 然后，锁存器被设置为通过响应于激活的控制信号将锁存器耦合到第一电压供应端子来存储第一逻辑值。 当控制信号被去激活时，锁存器从第一电压提供端被去耦合并耦合到非易失性存储单元。 如果非易失性存储单元被编程，则锁存器耦合到第二电压供应端，从而在锁存器中存储第二逻辑值。 如果非易失性存储单元被擦除，则锁存器与第二电压源端子隔离，并且第一逻辑值保持存储在锁存器中。 锁存器也可以通过一个或多个存取晶体管直接写入，从而便于测试。

公开(公告)号：US20140060609A1

公开(公告)日：2014-03-06

申请号：US13647152

申请日：2012-10-08

申请人： PRABHAT KUMAR ,  Sunhom Paak ,  James M. Gee

发明人： PRABHAT KUMAR ,  Sunhom Paak ,  James M. Gee

IPC分类号： H01L31/05 ,  H01L31/18

CPC分类号： H01L31/0504 ,  H01L31/0512 ,  Y02E10/50

摘要： Apparatuses and assembly methods are provided for a monolithic solar cell panel assembly. The assembly comprises an array of solar cells having front electrical contacts and back electrical contacts, wherein a first set of the solar cells in the array are aligned to be electrically connected in series through a back circuit sheet having an array of back metal contacts connected to corresponding back electrical contacts on the first set of solar cells, and through a front circuit sheet having an array of front metal contacts connected to corresponding front electrical contacts on the first set of solar cells. Electrical connections may be made in a lamination step, in which an encapsulant polymer flows into gaps and an interconnect material connects the circuits to form the monolithic solar cell panel assembly.

摘要翻译： 为单片太阳能电池板组件提供了装置和装配方法。 组件包括具有前电触头和背电触头的太阳能电池阵列，其中阵列中的第一组太阳能电池被对准以通过背电路片串联电连接，所述背板具有连接到 在第一组太阳能电池上的相应的后部电触点，以及通过连接到第一组太阳能电池组上的对应的前部电触点的前部金属触点阵列的前部电路板。 电连接可以在层压步骤中进行，其中密封剂聚合物流入间隙，并且互连材料连接电路以形成单片太阳能电池面板组件。

公开(公告)号：US20110272008A1

公开(公告)日：2011-11-10

申请号：US13101871

申请日：2011-05-05

申请人： Hemant P. Mungekar ,  Mukul Agrawal ,  Michael P. Stewart ,  Timothy W. Weidman ,  Rohit Mishra ,  Sunhom Paak

发明人： Hemant P. Mungekar ,  Mukul Agrawal ,  Michael P. Stewart ,  Timothy W. Weidman ,  Rohit Mishra ,  Sunhom Paak

IPC分类号： H01L31/02 ,  H01L31/18 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L31/02168 ,  H01L31/056 ,  Y02E10/52

摘要： Embodiments of the invention generally provide methods for forming a multilayer rear surface passivation layer on a solar cell substrate. The method includes forming a silicon oxide sub-layer having a net charge density of less than or equal to 2.1×1011 Coulombs/cm2 on a rear surface of a p-type doped region formed in a substrate comprising semiconductor material, the rear surface opposite a light receiving surface of the substrate and forming a silicon nitride sub-layer on the silicon oxide sub-layer. Embodiments of the invention also include a solar cell device that may be manufactured according methods disclosed herein.

摘要翻译： 本发明的实施例通常提供在太阳能电池基板上形成多层后表面钝化层的方法。 该方法包括在形成于包含半导体材料的衬底的p型掺杂区的后表面上形成净电荷密度小于或等于2.1×10 11库仑/ cm 2的氧化硅子层， 所述衬底的光接收表面并在所述氧化硅子层上形成氮化硅子层。 本发明的实施例还包括可以根据本文公开的方法制造的太阳能电池装置。

公开(公告)号：US07312625B1

公开(公告)日：2007-12-25

申请号：US11449197

申请日：2006-06-08

申请人： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

发明人： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

IPC分类号： G01R31/00

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/2858

摘要： A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

摘要翻译： 描述了用于制造用于超大规模集成（“VLSI”）处理的晶体管的测试电路及其使用方法。 晶体管形成阵列。 第一解码器耦合到晶体管的栅极并被配置为选择性地将电压传递到栅极。 第二解码器耦合到晶体管的漏极区域并且被配置为选择性地将电压传递到晶体管的漏极区域。 第三解码器耦合到晶体管的源极区域并且被配置为选择性地将电压传递到晶体管的源极区域。 第四解码器耦合到晶体管的体区，并且被配置为选择性地将电压传递到晶体管的体区。

公开(公告)号：US07301811B1

公开(公告)日：2007-11-27

申请号：US10990173

申请日：2004-11-15

申请人： Sunhom Paak

发明人： Sunhom Paak

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C14/00

摘要： A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in a first polysilicon layer, and a tunnel window formed in a tunnel oxide area, wherein the tunnel oxide area is covered by at least a portion of the floating gate. The control gate may control charge on the floating gate, and may be formed in a second polysilicon layer, wherein the second polysilicon layer is above the first polysilicon layer.

摘要翻译： 成本有效的非易失性存储单元可以包括逆变器，耦合到逆变器的访问门，用于控制对存储单元的访问以及控制门。 逆变器可以包括在反相器的输入处的浮动栅极，形成在第一多晶硅层中的浮置栅极和形成在隧道氧化物区域中的隧道窗口，其中隧道氧化物区域被浮动的至少一部分覆盖 门。 控制栅极可以控制浮置栅极上的电荷，并且可以形成在第二多晶硅层中，其中第二多晶硅层在第一多晶硅层之上。

公开(公告)号：US07760538B1

公开(公告)日：2010-07-20

申请号：US12042264

申请日：2008-03-04

申请人： Sunhom Paak

发明人： Sunhom Paak

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C11/412 ,  G11C13/0004 ,  G11C14/0081 ,  G11C14/009

摘要： A non-volatile static random access memory (“SRAM”) cell using variable resistance random access memory (“RAM”) cells is described. A memory tri-cell includes an SRAM cell with a first charge node and a second charge node. A first variable resistance random access memory cell is coupled between the first charge node and a supply voltage bus. A second variable resistance random access memory cell is coupled between the first charge node and a ground bus. A first control gate is coupled between the supply voltage bus and the first variable resistance random access memory cell. A second control gate is coupled between the ground bus and the second variable resistance random access memory cell.

摘要翻译： 描述了使用可变电阻随机存取存储器（“RAM”）单元的非易失性静态随机存取存储器（“SRAM”）单元。 存储器三单元包括具有第一充电节点和第二充电节点的SRAM单元。 第一可变电阻随机存取存储器单元耦合在第一充电节点和电源电压母线之间。 第二可变电阻随机存取存储器单元耦合在第一充电节点和接地总线之间。 第一控制栅极耦合在电源电压总线和第一可变电阻随机存取存储单元之间。 第二控制栅极耦合在接地总线和第二可变电阻随机存取存储单元之间。