公开(公告)号：US08564023B2

公开(公告)日：2013-10-22

申请号：US12043914

申请日：2008-03-06

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H01L23/52

CPC classification number: H01L27/101 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

Abstract translation: MOS熔丝的至少一个MOS参数的特征在于提供至少一个MOS参数参考值。 然后，通过向熔丝端子施加编程信号来编程MOS熔丝，使得编程电流流过熔丝链。 测量熔丝电阻以提供与第一逻辑值相关联的测量的熔丝电阻。 测量编程的MOS保险丝的MOS参数，以提供测量的MOS参数值。 将测量的MOS参数值与参考MOS参数值进行比较，以确定MOS熔丝的第二逻辑值，并且基于比较输出位值。

公开(公告)号：US07834659B1

公开(公告)日：2010-11-16

申请号：US12043103

申请日：2008-03-05

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H03K19/173

CPC classification number: G11C17/18

Abstract: E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.

Abstract translation: 通过对多个E保险丝应用第一编程脉冲将多个E保险丝编程到第一状态来编程E熔丝存储器阵列中的电子熔丝; 然后将第二编程脉冲施加到所述多个E熔丝中的至少一个选定的E熔丝，以将所选择的E熔丝编程到第二状态。

公开(公告)号：US07567449B2

公开(公告)日：2009-07-28

申请号：US11588775

申请日：2006-10-27

Applicant: Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

Inventor： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

IPC: G11C17/00

CPC classification number: G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

Abstract translation: 具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。 耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。 在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

公开(公告)号：US07381620B1

公开(公告)日：2008-06-03

申请号：US11371023

申请日：2006-03-09

Applicant: Boon-Yong Ang ,  Hidehiko Shiraiwa ,  Simon S. Chan ,  Harpreet K. Sachar ,  Mark Randolph

Inventor： Boon-Yong Ang ,  Hidehiko Shiraiwa ,  Simon S. Chan ,  Harpreet K. Sachar ,  Mark Randolph

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3162 ,  H01L27/11568

Abstract: A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.

Abstract translation: 一种方法包括在包含氧的处理室中形成半导体器件的至少一部分，并从处理室中去除基本上所有的氧。 该方法还包括在处理室内形成半导体器件的剩余部分而不存在氧气。

公开(公告)号：US07122465B1

公开(公告)日：2006-10-17

申请号：US11003208

申请日：2004-12-02

Applicant: Boon-Yong Ang ,  Cinti Xiaohua Chen ,  Simon S. Chan ,  Inkuk Kang

Inventor： Boon-Yong Ang ,  Cinti Xiaohua Chen ,  Simon S. Chan ,  Inkuk Kang

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/3212 ,  H01L21/7684

Abstract: According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.

Abstract translation: 根据一个示例性实施例，一种方法包括蚀刻ILD层中的沟槽的步骤，所述沟槽具有侧壁和底表面。 该方法还包括确定沟槽的侧壁的高度。 该方法还包括用互连金属填充沟槽，使得互连金属在沟槽之上延伸。 根据该示例性实施例，该方法还包括执行CMP处理以去除互连金属的一部分。 在本发明中，利用沟槽侧壁的高度来控制在CMP工艺中执行的抛光量。 沟槽中的互连金属的剩余部分形成互连线，其中通过利用沟槽的侧壁的高度来控制互连线的厚度以控制CMP工艺中的抛光量。

公开(公告)号：US20050040477A1

公开(公告)日：2005-02-24

申请号：US10643461

申请日：2003-08-18

Applicant: Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

Inventor： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

IPC: H01L29/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

Abstract: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

Abstract translation: 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

公开(公告)号：US07923811B1

公开(公告)日：2011-04-12

申请号：US12043910

申请日：2008-03-06

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H01L23/52

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.

Abstract translation: 电子熔丝（“E-fuse”）单元形成在半导体衬底上。 电子熔断器单元具有熔丝元件，熔丝链从第一熔丝端子穿过厚电介质结构延伸到第二熔丝端子。 第一和第二熔丝端子通过薄的电介质层与半导体衬底分离。

公开(公告)号：US20080101146A1

公开(公告)日：2008-05-01

申请号：US11588775

申请日：2006-10-27

Applicant: Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

Inventor： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

IPC: G11C17/18

CPC classification number: G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

Abstract translation: 具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。 耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。 在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

公开(公告)号：US06974989B1

公开(公告)日：2005-12-13

申请号：US10841933

申请日：2004-05-06

Applicant: Cinti X. Chen ,  Boon-Yong Ang ,  Hajime Wada ,  Sameer S. Haddad ,  Inkuk Kang

Inventor： Cinti X. Chen ,  Boon-Yong Ang ,  Hajime Wada ,  Sameer S. Haddad ,  Inkuk Kang

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11568

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.

Abstract translation: 根据一个示例性实施例，一种结构包括基底。 该结构还包括位于基板上的至少一个存储单元。 所述结构还包括位于所述至少一个存储单元上并位于所述衬底之上的第一层间介电层。 该结构还包括位于第一层间介电层上的氧化物覆盖层。 根据该示例性实施例，该结构还包括位于氧化物覆盖层上的包含TCS氮化物的蚀刻停止层，其中蚀刻停止层阻挡UV辐射。 该结构还包括位于蚀刻停止层上的第二层间介电层。 该结构还可以包括位于第二层间电介质层和蚀刻停止层中的沟槽，其中沟槽被铜填充。 该结构还可以包括位于第二层间介电层上的抗反射涂层。

公开(公告)号：US20050101147A1

公开(公告)日：2005-05-12

申请号：US10705347

申请日：2003-11-08

Applicant: Catherine Labelle ,  Boon-Yong Ang ,  Joong Jeon ,  Allison Holbrook ,  Qi Xiang ,  Huicai Zhong

Inventor： Catherine Labelle ,  Boon-Yong Ang ,  Joong Jeon ,  Allison Holbrook ,  Qi Xiang ,  Huicai Zhong

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/28202 ,  H01L21/28176 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/518

Abstract: According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.

Abstract translation: 根据一个示例性实施例，一种在衬底上形成场效应晶体管的方法，其中衬底包括位于衬底上方的高k电介质层和位于高k电介质层上方的栅电极层，包括步骤 蚀刻栅极电极层和高k电介质层以形成栅极叠层，其中栅极堆叠包括位于衬底上方的高k电介质段和位于高k电介质段上方的栅电极段。 根据该示例性实施例，该方法还包括在栅极堆叠上执行氮化处理。 氮化工艺可以通过例如利用等离子体来氮化栅堆叠的侧壁来进行，其中等离子体包括氮。 例如，氮化处理可以使氮进入高k电介质段，并在高k电介质段中形成氧扩散阻挡层。