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    Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing
    2.
    发明授权
    Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing 有权
    用于保护记忆细胞免受后期处理中的紫外线辐射损伤和紫外线辐射诱导的充电的结构和方法

    公开(公告)号：US06974989B1

    公开(公告)日：2005-12-13

    申请号：US10841933

    申请日：2004-05-06

    申请人： Cinti X. Chen ,  Boon-Yong Ang ,  Hajime Wada ,  Sameer S. Haddad ,  Inkuk Kang

    发明人： Cinti X. Chen ,  Boon-Yong Ang ,  Hajime Wada ,  Sameer S. Haddad ,  Inkuk Kang

    IPC分类号： H01L21/8246 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.

    摘要翻译： 根据一个示例性实施例，一种结构包括基底。 该结构还包括位于基板上的至少一个存储单元。 所述结构还包括位于所述至少一个存储单元上并位于所述衬底之上的第一层间介电层。 该结构还包括位于第一层间介电层上的氧化物覆盖层。 根据该示例性实施例，该结构还包括位于氧化物覆盖层上的包含TCS氮化物的蚀刻停止层，其中蚀刻停止层阻挡UV辐射。 该结构还包括位于蚀刻停止层上的第二层间介电层。 该结构还可以包括位于第二层间电介质层和蚀刻停止层中的沟槽，其中沟槽被铜填充。 该结构还可以包括位于第二层间介电层上的抗反射涂层。

    Method for achieving increased control over interconnect line thickness across a wafer and between wafers
    4.
    发明授权
    Method for achieving increased control over interconnect line thickness across a wafer and between wafers 有权
    用于实现跨晶片和晶片之间的互连线厚度的增加的控制的方法

    公开(公告)号：US07122465B1

    公开(公告)日：2006-10-17

    申请号：US11003208

    申请日：2004-12-02

    申请人： Boon-Yong Ang ,  Cinti Xiaohua Chen ,  Simon S. Chan ,  Inkuk Kang

    发明人： Boon-Yong Ang ,  Cinti Xiaohua Chen ,  Simon S. Chan ,  Inkuk Kang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/3212 ,  H01L21/7684

    摘要： According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.

    摘要翻译： 根据一个示例性实施例，一种方法包括蚀刻ILD层中的沟槽的步骤，所述沟槽具有侧壁和底表面。 该方法还包括确定沟槽的侧壁的高度。 该方法还包括用互连金属填充沟槽，使得互连金属在沟槽之上延伸。 根据该示例性实施例，该方法还包括执行CMP处理以去除互连金属的一部分。 在本发明中，利用沟槽侧壁的高度来控制在CMP工艺中执行的抛光量。 沟槽中的互连金属的剩余部分形成互连线，其中通过利用沟槽的侧壁的高度来控制互连线的厚度以控制CMP工艺中的抛光量。

    Field effect transistor having increased carrier mobility
    6.
    发明授权
    Field effect transistor having increased carrier mobility 有权
    场效应晶体管的载流子迁移率增加

    公开(公告)号：US07923785B2

    公开(公告)日：2011-04-12

    申请号：US10643461

    申请日：2003-08-18

    申请人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    发明人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

    摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

    摘要翻译： 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

    Method for integrating a high-k gate dielectric in a transistor fabrication process
    7.
    发明申请
    Method for integrating a high-k gate dielectric in a transistor fabrication process 审中-公开
    在晶体管制造工艺中集成高k栅极电介质的方法

    公开(公告)号：US20050101147A1

    公开(公告)日：2005-05-12

    申请号：US10705347

    申请日：2003-11-08

    申请人： Catherine Labelle ,  Boon-Yong Ang ,  Joong Jeon ,  Allison Holbrook ,  Qi Xiang ,  Huicai Zhong

    发明人： Catherine Labelle ,  Boon-Yong Ang ,  Joong Jeon ,  Allison Holbrook ,  Qi Xiang ,  Huicai Zhong

    IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/28202 ,  H01L21/28176 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/518

    摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.

    摘要翻译： 根据一个示例性实施例，一种在衬底上形成场效应晶体管的方法，其中衬底包括位于衬底上方的高k电介质层和位于高k电介质层上方的栅电极层，包括步骤 蚀刻栅极电极层和高k电介质层以形成栅极叠层，其中栅极堆叠包括位于衬底上方的高k电介质段和位于高k电介质段上方的栅电极段。 根据该示例性实施例，该方法还包括在栅极堆叠上执行氮化处理。 氮化工艺可以通过例如利用等离子体来氮化栅堆叠的侧壁来进行，其中等离子体包括氮。 例如，氮化处理可以使氮进入高k电介质段，并在高k电介质段中形成氧扩散阻挡层。

    Detecting heat generating failures in unpassivated semiconductor devices
    8.
    发明授权
    Detecting heat generating failures in unpassivated semiconductor devices 失效
    检测未激活半导体器件中的发热故障

    公开(公告)号：US06866416B1

    公开(公告)日：2005-03-15

    申请号：US10635996

    申请日：2003-08-07

    申请人： Mehrdad Mahanpour ,  Alice H. Choi ,  Mohammad Massoodi ,  Boon-Yong Ang

    发明人： Mehrdad Mahanpour ,  Alice H. Choi ,  Mohammad Massoodi ,  Boon-Yong Ang

    IPC分类号： G01N25/72 ,  G01N33/00 ,  G01N25/00

    CPC分类号： G01N25/72 ,  G01N2033/0095

    摘要： A method and semiconductor device for detecting a heat generating failure in an unpassivated semiconductor device. The semiconductor device has an unpassivated surface and a heat generating failure, e.g., short circuit. A coating may be applied to the unpassivated surface of the semiconductor device. The coating may be non-electrically conducting and capable of localizing heat generated by the failure in a particular area. The semiconductor device may be biased. The failure may then be detected by detecting a location of the heat generated by the failure in the coating.

    摘要翻译： 一种用于检测未通过半导体器件的发热故障的方法和半导体器件。 半导体器件具有未钝化的表面和发热故障，例如短路。 可以将涂层施加到半导体器件的未钝化表面。 涂层可以是非导电的并且能够定位由特定区域中的故障产生的热量。 半导体器件可能被偏置。 然后可以通过检测由涂层中的故障产生的热的位置来检测故障。

    Field effect transistor having increased carrier mobility
    9.
    发明申请
    Field effect transistor having increased carrier mobility 有权
    场效应晶体管具有增加的载流子迁移率

    公开(公告)号：US20050040477A1

    公开(公告)日：2005-02-24

    申请号：US10643461

    申请日：2003-08-18

    申请人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    发明人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    IPC分类号： H01L29/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

    摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

    摘要翻译： 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。