公开(公告)号：US20120008449A1

公开(公告)日：2012-01-12

申请号：US12979345

申请日：2010-12-28

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C5/14

CPC classification number: G11C11/417 ,  G11C11/413

Abstract: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

Abstract translation: 在待机模式和写入模式下，将存储单元阵列保持在低电压状态的SRAM，并在读取模式下将存储单元阵列电源电压提高到高电平。 一种SRAM，包括：至少一个存储单元电路，包括具有至少两个反相器的锁存电路，并且包括用于接收电力的两个电力接收端子; 以及供电电路，用于向存储单元电路提供电力，使得当数据被写入锁存电路时，锁存电路的电力接收端的电压低于预定的电压电平。 在一个实施例中，存储单元电路包括多个数据访问终端，并且数据访问终端分别由至少两个传输晶体管开关器件控制。

公开(公告)号：US20120008377A1

公开(公告)日：2012-01-12

申请号：US12985289

申请日：2011-01-05

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Yung-Wei Lin ,  Chien-Yu Lu ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C11/40 ,  G11C5/14

CPC classification number: G11C11/419

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract translation: 一种具有数据控制电源的静态随机存取存储器，其包括存储单元电路和至少一个写辅助电路，用于根据要写入存储单元电路的数据向存储单元电路供电。

公开(公告)号：US20110235444A1

公开(公告)日：2011-09-29

申请号：US13070977

申请日：2011-03-24

Applicant: Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

Inventor： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

IPC: G11C7/00

CPC classification number: G11C11/413

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Abstract translation: 提供SRAM写入系统及相关装置。 本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。 在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。 在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压 脉冲控制信号。

公开(公告)号：US07742327B2

公开(公告)日：2010-06-22

申请号：US12265042

申请日：2008-11-05

Applicant: Ching Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract translation: 为非对称存储单元中的背栅极控制提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

公开(公告)号：US20090067223A1

公开(公告)日：2009-03-12

申请号：US12265042

申请日：2008-11-05

Applicant: Ching Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract translation: 为非对称存储单元中的背栅极控制提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

公开(公告)号：US07492628B2

公开(公告)日：2009-02-17

申请号：US11933505

申请日：2007-11-01

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: Techniques are provided for a computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An encoded inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract translation: 为使用背栅控制的非对称存储单元编码存储器的计算机可读介质提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 编码的本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

公开(公告)号：US20080278992A1

公开(公告)日：2008-11-13

申请号：US12140366

申请日：2008-06-17

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

Abstract translation: 提供了在不对称存储单元中采用独立门控制的技术。 诸如SRAM电路的存储器电路可以包括多个位线结构，与位线结构相交以形成多个单元位置的多个字线结构以及位于单元的多个非对称存储单元 位置。 每个非对称单元可以在相应的一个字线结构的控制下选择性地耦合到位线结构中的对应的一个。 每个单元可以包括多个场效应晶体管（FETS），并且FETS中的至少一个可以被配置为单独偏置的前门和后门。 一个栅极可以以预定的方式与另一个栅极分开偏置，以增强不对称单元的读取稳定性。

公开(公告)号：US07417889B2

公开(公告)日：2008-08-26

申请号：US11362612

申请日：2006-02-27

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

Abstract translation: 提供了在不对称存储单元中采用独立门控制的技术。 诸如SRAM电路的存储器电路可以包括多个位线结构，与位线结构相交以形成多个单元位置的多个字线结构以及位于单元的多个非对称存储单元 位置。 每个非对称单元可以在相应的一个字线结构的控制下选择性地耦合到位线结构中的对应的一个。 每个单元可以包括多个场效应晶体管（FETS），并且FETS中的至少一个可以被配置为单独偏置的前门和后门。 一个栅极可以以预定的方式与另一个栅极分开偏置，以增强不对称单元的读取稳定性。

公开(公告)号：US07342287B2

公开(公告)日：2008-03-11

申请号：US11184244

申请日：2005-07-19

Applicant: Ching-Te Chuang ,  Koushik K. Das ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

Inventor： Ching-Te Chuang ,  Koushik K. Das ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

IPC: H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092

Abstract: Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

Abstract translation: 公开了一种多阈值CMOS电路和一种设计这种电路的方法。 优选实施例组合MTCMOS方案和混合SOI外延CMOS结构。 通常，逻辑晶体管（nFET和pFET都）放置在SOI中，优选地以高性能，高密度的UTSOI; 而集管或页脚由大量外延CMOS器件制成，具有或不具有自适应阱偏置方案。 逻辑晶体管基于（100）SOI器件或超级HOT，头部器件处于具有或不具有自适应阱偏置方案的体（100）或（110）pFET中，并且脚踏器件处于本体（100）NFET中 或没有自适应井偏置方案。

公开(公告)号：US20060227595A1

公开(公告)日：2006-10-12

申请号：US11100893

申请日：2005-04-07

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: Disclosed is an eight transistor static random access memory (SRAM) device, comprising first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of transistors, and has a respective data node. Each of a first and a second of the access transistors has a source, a drain, a front gate, and a back gate. The first access transistor is coupled to the first bit line, and the second access transistor is coupled to the first complement bit line. The back gate of the first access transistor is coupled to the data node of the first inverter; and the back gate of the second access transistor is coupled to the data node of the second inverter. This increases the difference between the threshold voltages of the first and second access transistors.

Abstract translation: 公开了一种八晶体管静态随机存取存储器（SRAM）器件，包括第一和第二反相器，第一位线，第一补码位线，一对写入存取晶体管和一对读存取晶体管。 第一和第二反相器中的每一个包括相应的晶体管对，并具有相应的数据节点。 第一和第二存取晶体管中的每一个具有源极，漏极，前栅极和后栅极。 第一存取晶体管耦合到第一位线，第二存取晶体管耦合到第一补码位线。 第一存取晶体管的背栅极耦合到第一反相器的数据节点; 并且第二存取晶体管的背栅极耦合到第二反相器的数据节点。 这增加了第一和第二存取晶体管的阈值电压之间的差异。