公开(公告)号：US5307007A

公开(公告)日：1994-04-26

申请号：US963093

申请日：1992-10-19

Applicant: Chung-Yu Wu ,  Shu-Yuan Chin

Inventor： Chung-Yu Wu ,  Shu-Yuan Chin

IPC: G05F3/26 ,  G05F3/30 ,  G05F3/16

CPC classification number: G05F3/30 ,  G05F3/26

Abstract: Precise CMOS bandgap voltage and current references which uses the difference of MOS source-gate voltages to perform efficient curvature compensation are proposed and analyzed. Applying the developed design strategies, bandgap voltage references (BVR) with a temperature drift below 10 ppm/.degree.C. and a power supply drift below 10 ppm/V can be realized. For bandgap current references, both drifts can be under 15 ppm. An experimental BVR chip shows an average drift of 5.5 ppm/.degree.C. from -60.degree. C. to 150.degree. C. and 25 .mu.V/V for supply voltages between 5 V and 15 V at 25.degree. C. Due to novel curvature compensation, the circuit structure of the proposed references is simple and both chip area and power consumption are small.

Abstract translation: 提出并分析了精确的CMOS带隙电压和电流参考，其使用MOS源极栅极电压的差异来执行有效的曲率补偿。 应用开发的设计策略，温度漂移低于10 ppm /℃的带隙电压基准（BVR）。 并且可以实现低于10ppm / V的电源漂移。 对于带隙电流参考，两个漂移都可以在15 ppm以下。 实验性BVR芯片显示出5.5ppm /℃的平均漂移。 从-60摄氏度到150摄氏度和25摄氏度（V / V），电源电压在25摄氏度在25摄氏度之间。由于新的曲率补偿，所提出的参考文献的电路结构简单， 芯片面积和功耗都很小。

公开(公告)号：US08928245B2

公开(公告)日：2015-01-06

申请号：US13594597

申请日：2012-08-24

Applicant: Chung-Yu Wu

Inventor： Chung-Yu Wu

IPC: H05B41/36

CPC classification number: G09G3/14 ,  G09G3/32 ,  G09G2320/0247 ,  G09G2320/064

Abstract: A driving circuit comprising a control unit, a current control unit, a pulse width modulation control unit and a current driving unit is described. The control unit provides a first control signal and a second control signal. The current control unit is connected to the control unit, and converts a reference current into a plurality of current setting signals based on a data signal and the first control signal. The pulse width modulation control unit is connected to the control unit and outputs a pulse signal based on the data signal and the second control signal. The current driving unit is connected to the pulse width modulation control unit and drives the light emitting diode based on a driving current, wherein the control unit generates a continuous conduction time in a predetermined operation period based on the pulse signal and the current setting signals.

Abstract translation: 描述了包括控制单元，电流控制单元，脉宽调制控制单元和电流驱动单元的驱动电路。 控制单元提供第一控制信号和第二控制信号。 电流控制单元连接到控制单元，并且基于数据信号和第一控制信号将参考电流转换为多个电流设置信号。 脉宽调制控制单元连接到控制单元，并根据数据信号和第二控制信号输出脉冲信号。 电流驱动单元连接到脉宽调制控制单元，并基于驱动电流驱动发光二极管，其中控制单元基于脉冲信号和当前设置信号，在预定的运行周期内产生连续导通时间。

公开(公告)号：US20130147384A1

公开(公告)日：2013-06-13

申请号：US13594597

申请日：2012-08-24

Applicant: Chung-Yu WU

Inventor： Chung-Yu WU

IPC: H05B37/02

CPC classification number: G09G3/14 ,  G09G3/32 ,  G09G2320/0247 ,  G09G2320/064

Abstract: A driving circuit comprising a control unit, a current control unit, a pulse width modulation control unit and a current driving unit is described. The control unit provides a first control signal and a second control signal. The current control unit is connected to the control unit, and converts a reference current into a plurality of current setting signals based on a data signal and the first control signal. The pulse width modulation control unit is connected to the control unit and outputs a pulse signal based on the data signal and the second control signal. The current driving unit is connected to the pulse width modulation control unit and drives the light emitting diode based on a driving current, wherein the control unit generates a continuous conduction time in a predetermined operation period based on the pulse signal and the current setting signals

Abstract translation: 描述了包括控制单元，电流控制单元，脉宽调制控制单元和电流驱动单元的驱动电路。 控制单元提供第一控制信号和第二控制信号。 电流控制单元连接到控制单元，并且基于数据信号和第一控制信号将参考电流转换为多个电流设置信号。 脉宽调制控制单元连接到控制单元，并根据数据信号和第二控制信号输出脉冲信号。 电流驱动单元连接到脉宽调制控制单元，并基于驱动电流驱动发光二极管，其中控制单元基于脉冲信号和当前设置信号在预定运行周期中产生连续导通时间

公开(公告)号：US20090066389A1

公开(公告)日：2009-03-12

申请号：US12129237

申请日：2008-05-29

Applicant: Chung Yu Wu ,  Po Kang Lin ,  Li Ju Lin ,  Wen Chia Yang ,  Chen Wan

Inventor： Chung Yu Wu ,  Po Kang Lin ,  Li Ju Lin ,  Wen Chia Yang ,  Chen Wan

IPC: H03H11/16

CPC classification number: A61F9/08

Abstract: The invention discloses a power controlling apparatus for a biochip including M regions. Each region includes a plurality of cells respectively. The power controlling apparatus includes a pulse generating module, a combinational circuit, and M controlling modules. The pulse generating module generates a pulse. The combinational circuit receives the pulse and generates M controlling signals. Each controlling signal has a predetermined phase which is different from the phase of the other controlling signal. The M controlling modules are electrically connected to the combinational circuit. Each of the M controlling signals corresponds to and activates one of the M controlling modules to selectively power on one corresponding region of the M regions. The cells in the corresponding region which is powered have an action potential refractory time that is longer than the power-on interval of the corresponding region.

Abstract translation: 本发明公开了一种用于包括M个区域的生物芯片的功率控制装置。 每个区域分别包括多个单元。 功率控制装置包括脉冲发生模块，组合电路和M个控制模块。 脉冲发生模块产生脉冲。 组合电路接收脉冲并产生M个控制信号。 每个控制信号具有与另一个控制信号的相位不同的预定相位。 M个控制模块电连接到组合电路。 M个控制信号中的每一个对应于并激活M个控制模块中的一个，以选择性地对M个区域的一个对应区域供电。 被供电的相应区域中的电池具有比对应区域的通电间隔更长的动作电位难度时间。

公开(公告)号：US06697052B2

公开(公告)日：2004-02-24

申请号：US09985200

申请日：2001-11-02

Applicant: Chi-Ting Shen ,  Ming-Chieh Tsou ,  Yu-Meng Chang ,  Kuan-Hsun Huang ,  Li-Ju Lin ,  Chung-Yu Wu

Inventor： Chi-Ting Shen ,  Ming-Chieh Tsou ,  Yu-Meng Chang ,  Kuan-Hsun Huang ,  Li-Ju Lin ,  Chung-Yu Wu

IPC: G09G508

CPC classification number: G06F3/0317

Abstract: An optical mouse chip with silicon retina structure comprises an image sensor array, an accumulator and a comparing/selecting unit. The image sensor array senses a direction parameter of an image along each axis. The accumulator sums the direction parameters of the image along different axes. The comparing/selecting unit selects a largest one from the sum of direction parameters of the image along different axes to determine a moving direction of the image.

Abstract translation: 具有硅视网膜结构的光学鼠标芯片包括图像传感器阵列，累加器和比较/选择单元。 图像传感器阵列感测沿着每个轴的图像的方向参数。 累加器将不同轴的图像的方向参数相加。 比较/选择单元从沿着不同轴的图像的方向参数的总和中选择最大的一个，以确定图像的移动方向。

公开(公告)号：US6041105A

公开(公告)日：2000-03-21

申请号：US144438

申请日：1998-09-01

Applicant: Chung-Yu Wu ,  Ching-Piao Su

Inventor： Chung-Yu Wu ,  Ching-Piao Su

IPC: H04M11/06 ,  H04M11/00

CPC classification number: H04M11/06

Abstract: An external adapter circuitry is plugged into the printer port of a host computer to provide the utility of computer telephony for the host computer. The circuitry is housed in a compact box which is about the size of a common parallel port connector. The circuitry consists of a telephone line interface for receiving and sending signals from/to the telephone line; a printer port interface for sending data to and receiving data from the host computer; a couple of registers for latching signal-in and signal-out; a A/D converter for converting analog signals to digital signals; and a D/A converter for converting digitized signals to analog signals. More specially, the electricity of the entire circuitry is supplied from a signal-to-power converter which obtains voltages from the printer port. Therefore, the external adapter circuitry does not need a power line for external power supply.

Abstract translation: 外部适配器电路插入到主计算机的打印机端口中，为主计算机提供计算机电话的实用程序。 该电路容纳在一个紧凑的盒子中，其尺寸约为公共并行端口连接器的尺寸。 该电路由用于接收和发送信号到电话线的电话线路接口组成; 用于向主计算机发送数据并从主机接收数据的打印机端口接口; 用于锁存信号和信号的几个寄存器; 用于将模拟信号转换为数字信号的A / D转换器; 以及用于将数字化信号转换为模拟信号的D / A转换器。 更具体地说，整个电路的电力是从从打印机端口获得电压的信号 - 功率转换器提供的。 因此，外部适配器电路不需要用于外部电源的电源线。

公开(公告)号：US5576557A

公开(公告)日：1996-11-19

申请号：US422225

申请日：1995-04-14

Applicant: Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

Inventor： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0259 ,  H01L27/0251

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

Abstract translation: 公开了一种用于保护半导体集成电路（IC）器件的静电放电（ESD）电路。 一个ESD电路位于连接到一个引脚和IC的内部电路的每个I / O缓冲焊盘之间。 ESD电路连接到两个电源端子。 ESD电路包括第一和第二低电压触发SCR（LVTSCR），每个具有阳极，阴极，阳极栅极和阴极栅极。 第一SCR的阳极和阳极栅极连接到第一电源端子，第一SCR的阴极连接到其I / O缓冲焊盘，第一SCR的阴极栅极连接到第二电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的PMOS晶体管。 PMOS晶体管的栅极，源极和体积端子连接到第一电源端子，PMOS晶体管漏极端子连接到第一SCR的阴极栅极。 第二SCR的阴极和阴极栅极连接到第二电源端子。 第二SCR的阳极连接到其相关的I / O缓冲垫。 第二SCR的阳极栅极连接到第一电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的NMOS晶体管。 NMOS晶体管的栅极，源极和体积端子连接到第二个电源端子。 NMOS晶体管的漏极端子连接到第二SCR的阳极栅极。

公开(公告)号：US5378942A

公开(公告)日：1995-01-03

申请号：US71523

申请日：1993-06-03

Applicant: Chung-Yu Wu ,  Kuo-Hsing Cheng

Inventor： Chung-Yu Wu ,  Kuo-Hsing Cheng

IPC: H03K19/096 ,  H03K19/0948

CPC classification number: H03K19/0963

Abstract: A CMOS dynamic logic structure has a plurality of logic gates, and the logic gates includes type-1 and type-3 logic gates alternately connected with each other. Each logic gate is separated into a function unit and a driver unit. The function unit has a PMOS precharge transistor, and a logic tree block stacked with the PMOS precharge transistor. The driver unit has an NMOS evaluation transistor, and the NMOS evaluation transistor and the PMOS precharge transistor of the previous-stage logic gate is controlled by an identical clock in order not to be turned on simultaneously.

Abstract translation: CMOS动态逻辑结构具有多个逻辑门，并且逻辑门包括彼此交替连接的类型1和3型逻辑门。 每个逻辑门分成功能单元和驱动单元。 功能单元具有PMOS预充电晶体管和与PMOS预充电晶体管堆叠的逻辑树块。 驱动器单元具有NMOS评估晶体管，并且前级逻辑门的NMOS评估晶体管和PMOS预充电晶体管由相同的时钟控制，以便不同时导通。

公开(公告)号：US5289334A

公开(公告)日：1994-02-22

申请号：US978332

申请日：1992-11-18

Applicant: Ming-Dou Ker ,  Chung-Yuan Lee ,  Chung-Yu Wu

Inventor： Ming-Dou Ker ,  Chung-Yuan Lee ,  Chung-Yu Wu

IPC: H01L27/02 ,  H02H9/04 ,  H02H9/00 ,  H02H3/22

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L27/0259 ,  H02H9/046

Abstract: A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply terminals, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated components are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.

Abstract translation: 用于保护CMOS芯片免受静电放电（ESD）损坏的电路在被保护线路和两个电源端子VDD和VSS之间连接有四个SCR。 将SCR极化以对每个电源端子进行任一极性的ESD电流。 用于SCR和相关部件的双极晶体管以有利的方式布置在芯片中，这降低了输入/输出寄生电容并且提高了具有低ESD触发电压的所提出的电路的保护能力。