公开(公告)号：US5378942A

公开(公告)日：1995-01-03

申请号：US71523

申请日：1993-06-03

Applicant: Chung-Yu Wu ,  Kuo-Hsing Cheng

Inventor： Chung-Yu Wu ,  Kuo-Hsing Cheng

IPC: H03K19/096 ,  H03K19/0948

CPC classification number: H03K19/0963

Abstract: A CMOS dynamic logic structure has a plurality of logic gates, and the logic gates includes type-1 and type-3 logic gates alternately connected with each other. Each logic gate is separated into a function unit and a driver unit. The function unit has a PMOS precharge transistor, and a logic tree block stacked with the PMOS precharge transistor. The driver unit has an NMOS evaluation transistor, and the NMOS evaluation transistor and the PMOS precharge transistor of the previous-stage logic gate is controlled by an identical clock in order not to be turned on simultaneously.

Abstract translation: CMOS动态逻辑结构具有多个逻辑门，并且逻辑门包括彼此交替连接的类型1和3型逻辑门。 每个逻辑门分成功能单元和驱动单元。 功能单元具有PMOS预充电晶体管和与PMOS预充电晶体管堆叠的逻辑树块。 驱动器单元具有NMOS评估晶体管，并且前级逻辑门的NMOS评估晶体管和PMOS预充电晶体管由相同的时钟控制，以便不同时导通。

公开(公告)号：US08928245B2

公开(公告)日：2015-01-06

申请号：US13594597

申请日：2012-08-24

Applicant: Chung-Yu Wu

Inventor： Chung-Yu Wu

IPC: H05B41/36

CPC classification number: G09G3/14 ,  G09G3/32 ,  G09G2320/0247 ,  G09G2320/064

Abstract: A driving circuit comprising a control unit, a current control unit, a pulse width modulation control unit and a current driving unit is described. The control unit provides a first control signal and a second control signal. The current control unit is connected to the control unit, and converts a reference current into a plurality of current setting signals based on a data signal and the first control signal. The pulse width modulation control unit is connected to the control unit and outputs a pulse signal based on the data signal and the second control signal. The current driving unit is connected to the pulse width modulation control unit and drives the light emitting diode based on a driving current, wherein the control unit generates a continuous conduction time in a predetermined operation period based on the pulse signal and the current setting signals.

Abstract translation: 描述了包括控制单元，电流控制单元，脉宽调制控制单元和电流驱动单元的驱动电路。 控制单元提供第一控制信号和第二控制信号。 电流控制单元连接到控制单元，并且基于数据信号和第一控制信号将参考电流转换为多个电流设置信号。 脉宽调制控制单元连接到控制单元，并根据数据信号和第二控制信号输出脉冲信号。 电流驱动单元连接到脉宽调制控制单元，并基于驱动电流驱动发光二极管，其中控制单元基于脉冲信号和当前设置信号，在预定的运行周期内产生连续导通时间。

公开(公告)号：US06697052B2

公开(公告)日：2004-02-24

申请号：US09985200

申请日：2001-11-02

Applicant: Chi-Ting Shen ,  Ming-Chieh Tsou ,  Yu-Meng Chang ,  Kuan-Hsun Huang ,  Li-Ju Lin ,  Chung-Yu Wu

Inventor： Chi-Ting Shen ,  Ming-Chieh Tsou ,  Yu-Meng Chang ,  Kuan-Hsun Huang ,  Li-Ju Lin ,  Chung-Yu Wu

IPC: G09G508

CPC classification number: G06F3/0317

Abstract: An optical mouse chip with silicon retina structure comprises an image sensor array, an accumulator and a comparing/selecting unit. The image sensor array senses a direction parameter of an image along each axis. The accumulator sums the direction parameters of the image along different axes. The comparing/selecting unit selects a largest one from the sum of direction parameters of the image along different axes to determine a moving direction of the image.

Abstract translation: 具有硅视网膜结构的光学鼠标芯片包括图像传感器阵列，累加器和比较/选择单元。 图像传感器阵列感测沿着每个轴的图像的方向参数。 累加器将不同轴的图像的方向参数相加。 比较/选择单元从沿着不同轴的图像的方向参数的总和中选择最大的一个，以确定图像的移动方向。

公开(公告)号：US6041105A

公开(公告)日：2000-03-21

申请号：US144438

申请日：1998-09-01

Applicant: Chung-Yu Wu ,  Ching-Piao Su

Inventor： Chung-Yu Wu ,  Ching-Piao Su

IPC: H04M11/06 ,  H04M11/00

CPC classification number: H04M11/06

Abstract: An external adapter circuitry is plugged into the printer port of a host computer to provide the utility of computer telephony for the host computer. The circuitry is housed in a compact box which is about the size of a common parallel port connector. The circuitry consists of a telephone line interface for receiving and sending signals from/to the telephone line; a printer port interface for sending data to and receiving data from the host computer; a couple of registers for latching signal-in and signal-out; a A/D converter for converting analog signals to digital signals; and a D/A converter for converting digitized signals to analog signals. More specially, the electricity of the entire circuitry is supplied from a signal-to-power converter which obtains voltages from the printer port. Therefore, the external adapter circuitry does not need a power line for external power supply.

Abstract translation: 外部适配器电路插入到主计算机的打印机端口中，为主计算机提供计算机电话的实用程序。 该电路容纳在一个紧凑的盒子中，其尺寸约为公共并行端口连接器的尺寸。 该电路由用于接收和发送信号到电话线的电话线路接口组成; 用于向主计算机发送数据并从主机接收数据的打印机端口接口; 用于锁存信号和信号的几个寄存器; 用于将模拟信号转换为数字信号的A / D转换器; 以及用于将数字化信号转换为模拟信号的D / A转换器。 更具体地说，整个电路的电力是从从打印机端口获得电压的信号 - 功率转换器提供的。 因此，外部适配器电路不需要用于外部电源的电源线。

公开(公告)号：US5576557A

公开(公告)日：1996-11-19

申请号：US422225

申请日：1995-04-14

Applicant: Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

Inventor： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0259 ,  H01L27/0251

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

Abstract translation: 公开了一种用于保护半导体集成电路（IC）器件的静电放电（ESD）电路。 一个ESD电路位于连接到一个引脚和IC的内部电路的每个I / O缓冲焊盘之间。 ESD电路连接到两个电源端子。 ESD电路包括第一和第二低电压触发SCR（LVTSCR），每个具有阳极，阴极，阳极栅极和阴极栅极。 第一SCR的阳极和阳极栅极连接到第一电源端子，第一SCR的阴极连接到其I / O缓冲焊盘，第一SCR的阴极栅极连接到第二电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的PMOS晶体管。 PMOS晶体管的栅极，源极和体积端子连接到第一电源端子，PMOS晶体管漏极端子连接到第一SCR的阴极栅极。 第二SCR的阴极和阴极栅极连接到第二电源端子。 第二SCR的阳极连接到其相关的I / O缓冲垫。 第二SCR的阳极栅极连接到第一电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的NMOS晶体管。 NMOS晶体管的栅极，源极和体积端子连接到第二个电源端子。 NMOS晶体管的漏极端子连接到第二SCR的阳极栅极。

公开(公告)号：US5289334A

公开(公告)日：1994-02-22

申请号：US978332

申请日：1992-11-18

Applicant: Ming-Dou Ker ,  Chung-Yuan Lee ,  Chung-Yu Wu

Inventor： Ming-Dou Ker ,  Chung-Yuan Lee ,  Chung-Yu Wu

IPC: H01L27/02 ,  H02H9/04 ,  H02H9/00 ,  H02H3/22

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L27/0259 ,  H02H9/046

Abstract: A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply terminals, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated components are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.

Abstract translation: 用于保护CMOS芯片免受静电放电（ESD）损坏的电路在被保护线路和两个电源端子VDD和VSS之间连接有四个SCR。 将SCR极化以对每个电源端子进行任一极性的ESD电流。 用于SCR和相关部件的双极晶体管以有利的方式布置在芯片中，这降低了输入/输出寄生电容并且提高了具有低ESD触发电压的所提出的电路的保护能力。

公开(公告)号：US20120099193A1

公开(公告)日：2012-04-26

申请号：US13101547

申请日：2011-05-05

Applicant: Li-Chang Yang ,  Chung-Yu Wu ,  Zong-Huan Cai

Inventor： Li-Chang Yang ,  Chung-Yu Wu ,  Zong-Huan Cai

IPC: G02B27/22 ,  H01L33/08 ,  H01L33/48

CPC classification number: G02B27/2214 ,  G02B19/0028 ,  G02B19/0061 ,  G02B19/0066 ,  G02B27/22 ,  G02B27/2228 ,  G09F19/18 ,  H01L25/0753 ,  H01L27/15 ,  H01L33/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A Light Emitting Diode (LED) packaging structure comprises an LED die, a package body, and an optical element. The package body wraps the LED die, and the optical element is disposed on the package body. A light beam emitted by the LED die passes through the optical element and is split into a plurality of sub-light beams, and each of sub-light beams is individually projected onto an image plane corresponding to the optical element. Therefore, the LED packaging structure is applied to an LED stereoscopic display device, so that left eye and right eye of a viewer may respectively receive light beams emitted by different LED dies, so as to view a stereoscopic image, thereby solving a problem of a conventional stereoscopic display device that the stereoscopic image may be viewed in only a single viewable area.

Abstract translation: 发光二极管（LED）封装结构包括LED管芯，封装体和光学元件。 封装体包裹LED管芯，光学元件设置在封装主体上。 由LED管芯发射的光束通过光学元件并被分成多个子光束，并且每个子光束被分别投影到对应于光学元件的像平面上。 因此，LED封装结构被应用于LED立体显示装置，使得观察者的左眼和右眼可以分别接收由不同LED管芯发射的光束，以便观看立体图像，从而解决了 常规的立体显示装置，立体图像只能在单个可视区域中观看。

公开(公告)号：US08072280B2

公开(公告)日：2011-12-06

申请号：US12552509

申请日：2009-09-02

Applicant: Wei-Zen Chen ,  Chung-Yu Wu ,  Chi-Yao Yu

Inventor： Wei-Zen Chen ,  Chung-Yu Wu ,  Chi-Yao Yu

IPC: H03B5/08

CPC classification number: H03K3/354 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1293 ,  H03B5/1296

Abstract: A voltage-controlled oscillator comprises a variable inductor, a negative impedance circuit, an operating voltage source and a ground point. The variable inductor comprises a transformer and a transistor switch, the transformer comprising a primary side coil and a secondary side coil, the primary side coil comprising a first coil and a second coil, and the secondary side coil comprising a third coil and a fourth coil. The transistor switch is connected in parallel with the primary side coil to adjust an inductance value of the variable inductor based on a gate voltage. The negative impedance circuit is connected in parallel with the secondary side coil to compensate the power consumption of the voltage-controlled oscillator during oscillation. The operating voltage source is electrically connected between the third coil and the fourth coil, and the ground point is electrically connected between the first coil and the second coil.

Abstract translation: 压控振荡器包括可变电感器，负阻抗电路，工作电压源和接地点。 可变电感器包括变压器和晶体管开关，变压器包括初级侧线圈和次级侧线圈，初级侧线圈包括第一线圈和第二线圈，次级侧线圈包括第三线圈和第四线圈 。 晶体管开关与初级侧线圈并联连接，以根据栅极电压调节可变电感器的电感值。 负阻抗电路与次级侧线圈并联连接，以补偿振荡期间压控振荡器的功耗。 工作电压源电连接在第三线圈和第四线圈之间，并且接地点电连接在第一线圈和第二线圈之间。

公开(公告)号：US6072219A

公开(公告)日：2000-06-06

申请号：US34529

申请日：1998-03-03

Applicant: Ming-Dou Ker ,  Tung-Yang Chen ,  Chung-Yu Wu

Inventor： Ming-Dou Ker ,  Tung-Yang Chen ,  Chung-Yu Wu

IPC: H01L27/02 ,  H01L27/088 ,  H01L23/62 ,  H01L27/01

CPC classification number: H01L27/0251 ,  H01L27/088

Abstract: A substrate-triggering ESD protection circuit is provided for use on a deep-submicron integrated circuit for ESD protection of the integrated circuit. The ESD protection circuit is incorporated between an input end and the internal circuit of the integrated circuit formed on a substrate. The ESD protection circuit utilizes a featured substrate-triggering operation to trigger the ESD-protection transistors formed in N-wells of the substrate into conducting state so as to bypass the ESD current to the ground. The ESD protection circuit allows a simplified semiconductor structure to fabricate, while nonetheless providing an increased level of ESD protection capability for the deep-submicron integrated circuit.

Abstract translation: 提供了一种基板触发ESD保护电路，用于集成电路的ESD保护的深亚微米集成电路。 ESD保护电路结合在基板上形成的集成电路的输入端和内部电路之间。 ESD保护电路利用特征的基板触发操作来将形成在衬底的N阱中的ESD保护晶体管触发到导通状态，以便绕过ESD电流到地。 ESD保护电路允许制造简化的半导体结构，同时为深亚微米集成电路提供更高水平的ESD保护能力。

公开(公告)号：US5631793A

公开(公告)日：1997-05-20

申请号：US523653

申请日：1995-09-05

Applicant: Ming-Dou Ker ,  Chung-Yu Wu ,  Tao Cheng ,  Chau-Neng Wu ,  Ta-Lee Yu

Inventor： Ming-Dou Ker ,  Chung-Yu Wu ,  Tao Cheng ,  Chau-Neng Wu ,  Ta-Lee Yu

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0251

Abstract: The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.

Abstract translation: 本发明涉及用于保护IC的内部电路和/或输出缓冲器免受ESD电流损坏的电容器对偶静电放电（ESD）保护电路。 根据本发明的电容耦合ESD保护电路包括用于旁路ESD电流的ESD旁路装置，用于将一部分电压耦合到ESD旁路装置的电容器耦合电路和用于保持ESD电压的电位调节装置 在低电位电平下为内部电路传输。 通过使用本ESD保护电路，可以降低回跳击穿电压，以保护内部电路的非常薄的栅极氧化物，特别是在亚微米CMOS技术中。