公开(公告)号：US06674679B1

公开(公告)日：2004-01-06

申请号：US10262051

申请日：2002-10-01

Applicant: Frederick A. Perner ,  Anthony P. Holden

Inventor： Frederick A. Perner ,  Anthony P. Holden

IPC: G11C706

CPC classification number: G11C7/062 ,  G11C11/1673 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/063 ,  G11C2213/77

Abstract: An adjustable current mode differential sense amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier. When a second bias voltage is applied to the memory and reference cells in order to determine the memory cell value, the amplifier is able to sense slight changes in the currents or voltages associated with the selected memory cell and the reference cell and compare them to determine the state of the memory cell. This increased sensitivity enables the amplifier to have a substantially increased dynamic range without introducing components that might adversely affect the memory circuitry parameters. The memory cell array being sensed has equi-potential isolation for all unselected memory cells, thereby minimizing sneak currents through the unselected memory cells.

Abstract translation: 可调电流模式差分读出放大器设置为与选定的存储单元和具有预定值的参考单元通信。 放大器能够检测与所选存储单元相关联的电流和电压变化，并将其与参考单元相关的电流和电压变化进行比较。 可以通过修改与施加到放大器中的选定晶体管的背栅极偏置相关的阈值电压来改变感测放大器的工作点。 当将第一偏置电压施加到所选择的存储器单元以便最大化放大器的灵敏度时，该调整能力使得读出放大器的电流或电压被设置。 当第二偏置电压施加到存储器和参考单元以便确定存储单元值时，放大器能够感测与所选择的存储器单元和参考单元相关联的电流或电压的轻微变化，并将其进行比较以确定 存储单元的状态。 这种增加的灵敏度使得放大器具有显着增加的动态范围，而不引入可能不利地影响存储器电路参数的组件。 所感测的存储单元阵列对所有未选择的存储单元具有等电位隔离，从而最小化通过未选择存储单元的潜行电流。

公开(公告)号：US06667901B1

公开(公告)日：2003-12-23

申请号：US10426381

申请日：2003-04-29

Applicant: Frederick A. Perner ,  Manish Sharma ,  Manoj Bhattacharyya

Inventor： Frederick A. Perner ,  Manish Sharma ,  Manoj Bhattacharyya

IPC: G11C1115

CPC classification number: G11C11/1673 ,  G11C11/161

Abstract: A magnetic memory device includes a first magnetic tunnel junction having a first reference ferromagnetic layer; a second magnetic tunnel junction having a second reference ferromagnetic layer; and an electrically conductive spacer layer between the first and second reference layers. The first and second reference layers are antiferromagnetically coupled.

Abstract translation: 磁存储器件包括具有第一参考铁磁层的第一磁性隧道结; 具有第二参考铁磁层的第二磁性隧道结; 以及在第一和第二参考层之间的导电间隔层。 第一和第二参考层是反铁磁耦合的。

公开(公告)号：US06643213B2

公开(公告)日：2003-11-04

申请号：US10096542

申请日：2002-03-12

Applicant: Frederick A. Perner ,  Manoj Bhattacharyya

Inventor： Frederick A. Perner ,  Manoj Bhattacharyya

IPC: G11C800

CPC classification number: G11C11/16

Abstract: A magnetic memory includes a memory cell and a conductor wherein the memory cell is crossed by the conductor. A write pulse generator is coupled to the conductor and is configured to provide a discharge current to the conductor during a write operation of the memory cell.

Abstract translation: 磁存储器包括存储单元和导体，其中存储单元被导体交叉。 写入脉冲发生器耦合到导体并被配置为在存储器单元的写入操作期间向导体提供放电电流。

公开(公告)号：US06256247B1

公开(公告)日：2001-07-03

申请号：US09745103

申请日：2000-12-19

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C1115

CPC classification number: G11C11/15 ,  G11C11/1673 ,  G11C27/02

Abstract: Resistance of a memory cell element in a resistive cross point memory cell array is sensed by a read circuit including a differential amplifier, a first direct injection preamplifier and a second direct injection preamplifier. During a read operation, the first direct injection preamplifier is coupled to a first input node of the differential amplifier, and the second direct injection preamplifier is coupled to a second input node of the differential amplifier.

公开(公告)号：US6115019A

公开(公告)日：2000-09-05

申请号：US30245

申请日：1998-02-25

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3648 ,  G09G2300/0814 ,  G09G2300/0852 ,  G09G3/3614 ,  G09G3/3651 ,  G09G3/3659

Abstract: A display device and a method of driving liquid crystals in an array of pixels of the display device include providing dual port memory cells that isolate write operations to the pixels from read operations within the pixels. Preferably, each pixel has an array of integrated dual port memory cells, with the number of cells in the array being equal to the number of bits per pixel within each frame of pixel data. The dual port memory cell may be an electrical series connection of a bit-storage device having write access circuitry (e.g., a write access transistor) on one side and read access circuitry (e.g., two read access transistors) on the opposite side. Such a series connection of devices enables the rate of driving the liquid crystal to be set independently from the rate of receiving pixel data at the pixels.

Abstract translation: 在显示装置的像素阵列中驱动液晶的显示装置和方法包括提供将像素的写入操作与像素内的读取操作隔离的双端口存储单元。 优选地，每个像素具有集成双端口存储器单元的阵列，其中阵列中的单元数目等于像素数据的每帧内的每像素的位数。 双端口存储器单元可以是在一侧具有写入存取电路（例如，写存取晶体管）和位于相对侧的读访问电路（例如，两个读存取晶体管）的位存储器件的电串联连接。 这种装置的串联使得可以独立于在像素处接收像素数据的速率来设置驱动液晶的速率。

公开(公告)号：US5097206A

公开(公告)日：1992-03-17

申请号：US593703

申请日：1990-10-05

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G01R31/28 ,  G01R31/30 ,  G11C29/50

CPC classification number: G01R31/3004 ,  G11C29/50 ,  G11C2029/5006

Abstract: A built-in test circuit configuration for row based static CMOS integrated circuits using a control circuit and a plurality of switching circuits, each connecting VDD to a row power buss through a large pass transistor during normal operating modes and through a low current pull up transistor during the test mode of operation. Defect induced currents are detected by the OR'd outputs of the switching circuits connected to an OR function formed in the control circuit. Additional switching circuits are provided for supplying multiple main power supplies to each integrated circuit row. The switching and additional switching circuits may be physically configured beneath row end caps.

Abstract translation: 内置测试电路配置，用于使用控制电路和多个开关电路的行型静态CMOS集成电路，每个开关电路在正常工作模式下通过大通晶体管连接VDD至行电源总线，并通过低电流上拉晶体管 在测试操作模式下。 缺陷感应电流由连接到控制电路中形成的OR功能的开关电路的OR'输出检测。 提供附加的开关电路用于向每个集成电路行提供多个主电源。 开关和附加开关电路可以物理地配置在行端盖下方。

公开(公告)号：US07248306B2

公开(公告)日：2007-07-24

申请号：US10897533

申请日：2004-07-23

Applicant: Frederick A. Perner ,  Krzysztof Nauka

Inventor： Frederick A. Perner ,  Krzysztof Nauka

IPC: G02F1/136

CPC classification number: G02F1/1362 ,  G02F1/133305 ,  G02F1/1368 ,  G02F2001/136295

Abstract: A method of making a lower cost active matrix display. In a particular embodiment, the method includes providing at least one first conductor upon a substrate and depositing a gate dielectric upon the first conductor and substrate. At least one paired second conductor and a pixel electrode are deposited upon the gate dielectric, with the second conductor crossing the first conductor and with a narrow gap between the paired second conductor and the pixel electrode. A semiconductor material is deposited over the paired second conductor and pixel electrode, filling the narrow gap. The narrow gap shelters a portion of the semiconductor material, which serves as a semiconductor bridge capable of functioning either as an insulator or as a channel region of a field effect transistor. The remaining, unsheltered semiconductor material is removed. A liquid crystal layer is then deposited upon the paired second conductor, the pixel electrode and the sheltered semiconductor material, and a translucent conductor is deposited upon the liquid crystal display layer. An associated display is also provided.

Abstract translation: 制作成本较低的有源矩阵显示的方法。 在特定实施例中，该方法包括在衬底上提供至少一个第一导体并在第一导体和衬底上沉积栅极电介质。 至少一对成对的第二导体和像素电极沉积在栅极电介质上，其中第二导体与第一导体交叉并且在成对的第二导体和像素电极之间具有窄间隙。 半导体材料沉积在成对的第二导体和像素电极上，填充窄间隙。 窄间隙避开半导体材料的一部分，其用作能够用作场效应晶体管的绝缘体或沟道区的半导体桥。 剩余的未加帽的半导体材料被去除。 然后将液晶层沉积在成对的第二导体，像素电极和遮蔽半导体材料上，并且半透明导体沉积在液晶显示层上。 还提供了相关联的显示。

公开(公告)号：US07242199B2

公开(公告)日：2007-07-10

申请号：US11112795

申请日：2005-04-21

Applicant: R. Stanley Williams ,  Philip J Kuekes ,  Frederick A. Perner ,  Greg Snider ,  Duncan Stewart

Inventor： R. Stanley Williams ,  Philip J Kuekes ,  Frederick A. Perner ,  Greg Snider ,  Duncan Stewart

IPC: G01R27/08

CPC classification number: H05K7/1092 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.

Abstract translation: 在本发明的各种实施例中，在集成电路的互连层处引入可调电阻器，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或者在制造之后配置集成电路。 例如，当诸如晶体管的某些内部组件由于制造缺陷而没有指定的电子特性时，可以使用根据本发明的实施例的集成电路的互连层中包括的可调谐电阻的可变电阻的调整 以调整内部电压和/或电平以便改善有缺陷的部件。 在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。

公开(公告)号：US07180770B2

公开(公告)日：2007-02-20

申请号：US11089688

申请日：2005-03-24

Applicant: Frederick A. Perner ,  Janice Nickel ,  Lung Tran

Inventor： Frederick A. Perner ,  Janice Nickel ,  Lung Tran

IPC: G11C11/02

CPC classification number: G11C11/16 ,  G11C11/1675

Abstract: An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.

Abstract translation: 提供信息存储装置。 信息存储装置可以是包括自旋相关隧道（SDT）结或磁存储元件的电阻交叉点阵列的磁性随机存取存储器（MRAM）装置，其中字线沿着沿着SDT结的行和沿着 SDT路口的列。 本设计包括与相关联的磁存储元件串联连接的多个加热元件，每个加热元件包括二极管。 施加到磁存储元件和相关联的加热元件的电压导致反向电流流过二极管，从而从二极管产生热量并加热磁存储元件，从而有助于器件的写入功能。

公开(公告)号：US07145797B2

公开(公告)日：2006-12-05

申请号：US11003904

申请日：2004-12-03

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for writing to the magnetic memory cell, determining a maximal magnitude of write current for writing to the magnetic memory cell, and calculating the selected magnitude of magnetic memory cell write current based on the minimal magnitude of write current and the maximal magnitude of write current.

Abstract translation: 本发明包括用于选择磁存储单元写入电流的期望幅度的装置和方法。 该方法包括确定用于写入磁存储器单元的写入电流的最小幅度，确定用于写入磁存储单元的写入电流的最大幅度，以及基于最小幅度来计算所选择的磁存储单元写入电流的大小 写入电流和写入电流的最大幅度。