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    High data rate interface with improved link synchronization
    21.
    发明申请
    High data rate interface with improved link synchronization 有权
    高数据速率接口，改善了链路同步

    公开(公告)号：US20050204057A1

    公开(公告)日：2005-09-15

    申请号：US11008024

    申请日：2004-12-08

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: G06F15/16 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04L29/06 ,  H04M1/725

    CPC classification number: H04L65/1069 ,  H04L12/40071 ,  H04L12/40117 ,  H04L29/06027 ,  H04L65/4069 ,  H04L65/80 ,  H04L69/18 ,  H04L69/22 ,  H04M1/72527 ,  H04W56/00 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    METHODS AND SYSTEMS FOR OPERATING A COMPUTER VIA A LOW POWER ADJUNCT PROCESSOR
    23.
    发明申请
    METHODS AND SYSTEMS FOR OPERATING A COMPUTER VIA A LOW POWER ADJUNCT PROCESSOR 有权
    用于通过低功率ADJUNCT处理器操作计算机的方法和系统

    公开(公告)号：US20110055434A1

    公开(公告)日：2011-03-03

    申请号：US12551530

    申请日：2009-08-31

    Applicant: James PYERS ,  George WILEY ,  James J. WILLKIE ,  Brian STEELE ,  Apul NAHATA ,  Karthik Raj KALIANNAN

    Inventor： James PYERS ,  George WILEY ,  James J. WILLKIE ,  Brian STEELE ,  Apul NAHATA ,  Karthik Raj KALIANNAN

    IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F3/048 ,  G06F15/16 ,  G06F13/20

    CPC classification number: G06F1/3203 ,  G06F1/3293 ,  Y02D10/122

    Abstract: A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in “off,” “standby” or “sleep” modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.

    Abstract translation: 计算设备包括能够接管处理代替计算设备的中央处理单元（CPU）的低功率辅助处理器，诸如无线卡或子系统上的处理器。 在辅助处理器上操作计算设备从计算设备电池吸取更少的电力，从而能够在辅助处理器模式下进行扩展操作。 在此模式下，辅助处理器控制外设，并在CPU被关闭时提供系统功能，例如处于“关闭”，“待机”或“睡眠”模式。 在辅助处理器模式中，计算设备可以完成有用的任务，例如发送/接收电子邮件，显示电子文档和访问网络，同时从电池中抽取最小功率。 正常操作模式和辅助处理器模式之间的转换可能对用户来说是透明的。 这样的计算机可以立即显示，始终处于和始终连接的操作特征。

    Double data rate serial encoder
    24.
    发明申请
    Double data rate serial encoder 有权
    双数据率串行编码器

    公开(公告)号：US20060179384A1

    公开(公告)日：2006-08-10

    申请号：US11285397

    申请日：2005-11-23

    Applicant: George Wiley ,  Brian Steele ,  Curtis Musfeldt

    Inventor： George Wiley ,  Brian Steele ,  Curtis Musfeldt

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: H04J3/047 ,  H04L25/0264 ,  H04L25/028 ,  H04L25/0292

    Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

    Abstract translation: 提供双数据速率串行编码器。 串行编码器包括具有多个输入的多路复用器，耦合到多路复用器的输入的多个锁存器，使得锁存器能够更新其数据输入的启动器，以及用于选择多路复用器的多个输入之一的计数器 用于输出。 在另一方面，多路复用器在输入转换期间提供无毛刺输出。 多路复用器包括基于由计数器提供的输入选择序列的先验知识而优化的输出选择算法。

    Methods and systems for synchronous execution of commands across a communication link
    25.
    发明申请
    Methods and systems for synchronous execution of commands across a communication link 审中-公开
    通过通信链路同步执行命令的方法和系统

    公开(公告)号：US20060161691A1

    公开(公告)日：2006-07-20

    申请号：US11285400

    申请日：2005-11-23

    Applicant: Behnam Katibian ,  George Wiley

    Inventor： Behnam Katibian ,  George Wiley

    IPC: G06F3/00

    CPC classification number: G03B17/00

    Abstract: A method for synchronously executing a plurality of commands generated by a first module and executed at a second module, wherein the first and second modules communicate through a communication link, is provided. The method includes generating the commands at the first module, transmitting the commands through the link to the second module, and associating the execution time of the commands with an independent event at the second module. When the independent event is detected, the commands are executed synchronously at the second module. The method can be specifically applied to a baseband processor controlling a camera through a camera interface module, wherein the processor and the camera interface module are connected through an MDDI link. An example of a baseband processor controlling a camera through a Pathfinder camera module interface module is described. Specific built-in mechanisms of the camera module interface that enable flexible implementation of the method are also provided.

    Abstract translation: 一种用于同步执行由第一模块生成并在第二模块执行的多个命令的方法，其中第一和第二模块通过通信链路进行通信。 该方法包括在第一模块处生成命令，通过链路将命令发送到第二模块，并将命令的执行时间与第二模块处的独立事件相关联。 当检测到独立事件时，在第二模块上同步执行命令。 该方法可以专门应用于通过摄像机接口模块控制摄像机的基带处理器，其中处理器和摄像机接口模块通过MDDI链路连接。 描述了通过Pathfinder相机模块接口模块控制相机的基带处理器的示例。 还提供了能够灵活实现该方法的相机模块接口的特定内置机制。

    High data rate interface
    30.
    发明申请
    High data rate interface 有权
    高数据速率接口

    公开(公告)号：US20050120079A1

    公开(公告)日：2005-06-02

    申请号：US10938354

    申请日：2004-09-10

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04M1/725 ,  G06F15/16 ,  G06F13/00

    CPC classification number: H04L65/607 ,  H04L29/06027 ,  H04L69/14 ,  H04L69/18 ,  H04L69/22 ,  H04L69/24 ,  H04M1/72527 ,  Y02D50/30 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

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