公开(公告)号：US20080242022A1

公开(公告)日：2008-10-02

申请号：US11693829

申请日：2007-03-30

申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.

摘要翻译： 电子设备可以包括在电介质层内具有DSE的非易失性存储单元。 一方面，形成电子器件的方法可以包括将第一电荷存储材料植入和成核以形成DSE。 该过程还可以包括植入第二电荷储存材料并生长DSE，使得DSE包括第一和第二电荷存储材料。 在另一方面，形成电子器件的工艺可以包括在电介质层上形成半导体层，注入电荷存储材料，以及退火介电层。 在退火之后，基本上没有一种电荷存储材料保留在电介质层内的裸露区域内。 在第三方面，在介电层内，第一组DSE可以与第二组DSE间隔开，其中基本上没有DSE位于第一组DSE和第二组DSE之间。

公开(公告)号：US20080019178A1

公开(公告)日：2008-01-24

申请号：US11834391

申请日：2007-08-06

申请人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

发明人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/10

摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

摘要翻译： 电子电路可以包括第一存储单元和第二存储单元。 在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。 源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。 在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。 在另一方面，第一和第二存储器单元连接到相同的位线。 当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

公开(公告)号：US20070238249A1

公开(公告)日：2007-10-11

申请号：US11393287

申请日：2006-03-30

申请人： Craig Swift ,  Gowrishankar Chindalore ,  Paul Ingersoll

发明人： Craig Swift ,  Gowrishankar Chindalore ,  Paul Ingersoll

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C16/0458 ,  G11C2216/06 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825

摘要： A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.

摘要翻译： 半导体存储单元包括在半导体层中限定的第一沟槽下面的第一源极/漏极区域。 第二源极/漏极区域位于半导体层中的第二沟槽的下方。 第一沟槽中的第一选择栅极和第二沟槽中的第二选择栅极由选择栅极电介质排列。 电荷存储堆叠覆盖选择栅极，并且控制栅极覆盖堆叠。 DSE可以包括多晶硅的谨慎积累。 第一和第二选择栅极的上表面比第一和第二沟槽的上表面低。 控制栅极可以是垂直于选择栅极横穿并行进的连续控制栅极。 电池可以包括到半导体层的触点。 控制栅极可以包括覆盖第一选择栅极的第一控制栅极和覆盖第二选择栅极的第二控制栅极。

公开(公告)号：US20070105306A1

公开(公告)日：2007-05-10

申请号：US11267442

申请日：2005-11-04

申请人： Erwin Prinz ,  Gowrishankar Chindalore ,  Paul Ingersoll

发明人： Erwin Prinz ,  Gowrishankar Chindalore ,  Paul Ingersoll

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332

摘要： A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate (101) is provided, and first and second sets of memory stacks (103, 105, 107, and 109) are formed on the substrate, each memory stack comprising a control gate (111) and a layer of memory material (113). A source/drain region (123) is then formed between the first and second sets of memory stacks, and a silicide layer (125) is formed over the source/drain region.

摘要翻译： 本文提供了一种制造多位非易失性存储单元结构的方法。 根据该方法，提供半导体衬底（101），并且在衬底上形成第一和第二组存储堆叠（103,105,107和109），每个存储器堆包括控制栅极（111）和 一层记忆材料（113）。 然后在第一组和第二组存储器堆之间形成源极/漏极区（123），并且在源极/漏极区域上形成硅化物层（125）。

公开(公告)号：US20070030719A1

公开(公告)日：2007-02-08

申请号：US11197814

申请日：2005-08-05

申请人： Alexander Hoefler ,  Gowrishankar Chindalore

发明人： Alexander Hoefler ,  Gowrishankar Chindalore

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/112

摘要： A one time programmable (OTP) memory has two-bit cells for increasing density. Each cell has two select transistors and a programmable transistor in series between the two select transistors. The programmable transistor has two independent storage locations. One is between the gate and a first source/drain region and the second is between the gate and a second source/drain region. The storage locations are portions of the gate dielectric where the sources or drains overlap the gate and are independently programmed by selectively passing a programming current through them. The programming current is of sufficient magnitude and duration to permanently reduce the impedance by more than three orders of magnitude of the storage locations to be programmed. The programming current is limited in magnitude to avoid damage to other circuit elements and is preferably induced at least in part by applying a negative voltage to the gate of the programming transistor.

摘要翻译： 一次性可编程（OTP）存储器具有用于增加密度的两位单元。 每个单元具有两个选择晶体管和串联在两个选择晶体管之间的可编程晶体管。 可编程晶体管具有两个独立的存储位置。 一个在栅极和第一源极/漏极区域之间，第二栅极和第二源极/漏极区域之间。 存储位置是栅极电介质的部分，其中源极或漏极与栅极重叠，并且通过选择性地使编程电流通过它们而被独立地编程。 编程电流具有足够的幅度和持续时间，以将阻抗永久地减少待编程的存储位置的三个数量级以上。 编程电流的幅度受到限制以避免损坏其它电路元件，并且优选地通过向编程晶体管的栅极施加负电压至少部分地被感应。

公开(公告)号：US20070020831A1

公开(公告)日：2007-01-25

申请号：US11188583

申请日：2005-07-25

申请人： Gowrishankar Chindalore ,  Cheong Hong ,  Craig Swift

发明人： Gowrishankar Chindalore ,  Cheong Hong ,  Craig Swift

IPC分类号： H01L21/8234

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/7923 ,  H01L29/7926

摘要： A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

摘要翻译： 制造存储单元阵列的方法包括在半导体衬底中限定的第一沟槽下面的第一源极/漏极区域和在衬底中的第二沟槽下面的第二源极/漏极区域。 电荷存储堆叠线路中的每个沟槽，其中电荷存储堆叠包括不连续存储元件（DSE）层。 控制门覆盖在第一沟槽上。 控制栅极可以垂直于沟槽延伸并穿过第一和第二沟槽。 在另一实现中，控制栅极与沟槽平行地延伸。 存储单元可以包括占据第一和第二沟槽之间的衬底的上表面的一个或多个扩散区域。 扩散区域可以驻留在平行于沟槽的第一和第二控制栅极之间。 或者，一对扩散区域可以发生在垂直于沟槽的控制栅极的任一侧上。

公开(公告)号：US20070018222A1

公开(公告)日：2007-01-25

申请号：US11188999

申请日：2005-07-25

申请人： Michael Sadd ,  Ko-Min Chang ,  Gowrishankar Chindalore ,  Cheong Hong ,  Craig Swift

发明人： Michael Sadd ,  Ko-Min Chang ,  Gowrishankar Chindalore ,  Cheong Hong ,  Craig Swift

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825

摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.

摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。 电子设备还可以包括位于沟槽内的不连续存储元件的一部分。 电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。 电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。 在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

公开(公告)号：US20070018216A1

公开(公告)日：2007-01-25

申请号：US11188591

申请日：2005-07-25

申请人： Gowrishankar Chindalore ,  Paul Ingersoll ,  Craig Swift

发明人： Gowrishankar Chindalore ,  Paul Ingersoll ,  Craig Swift

IPC分类号： H01L29/94

CPC分类号： H01L29/7881 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 电子器件可以包括包括沟槽的衬底，其包括壁和底部并且从衬底的主表面延伸。 电子设备还可以包括不连续的存储元件，其中不连续存储元件的一部分至少位于沟槽内。 电子器件还可以包括第一栅极电极，其中不连续存储元件的部分的至少一部分位于第一栅电极和沟槽的壁之间。 电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。

公开(公告)号：US20060079051A1

公开(公告)日：2006-04-13

申请号：US10961014

申请日：2004-10-08

申请人： Gowrishankar Chindalore ,  Jane Yater

发明人： Gowrishankar Chindalore ,  Jane Yater

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Forming a non-volatile memory device includes providing a semiconductor substrate, forming a masking layer having a first plurality of openings overlying the semiconductor substrate, forming diffusion regions in the semiconductor substrate at locations determined by the masking layer, forming a dielectric within the first plurality of openings, removing the masking layer to form a second plurality of openings, forming sacrificial spacers along edges of the second plurality of openings and adjacent to the dielectric, forming a separating dielectric to separate the sacrificial spacers within each of the second plurality of openings, forming a sacrificial protection layer overlying the separating dielectric, removing the sacrificial spacers, removing the sacrificial protection layer, forming at least two memory storage regions within each of the second plurality of openings, and forming a common control electrode overlying the at least two memory storage regions. This device may be used, for example, in a VGA memory array.

摘要翻译： 形成非易失性存储器件包括提供半导体衬底，形成具有覆盖半导体衬底的第一多个开口的掩模层，在由掩模层确定的位置处在半导体衬底中形成扩散区，在第一多个 的开口，去除所述掩模层以形成第二多个开口，沿着所述第二多个开口的边缘并且邻近所述电介质形成牺牲隔离物，形成分离电介质以在所述第二多个开口的每一个内分离所述牺牲隔离物， 形成覆盖所述分离电介质的牺牲保护层，去除所述牺牲隔离物，去除所述牺牲保护层，在所述第二多个开口的每一个内形成至少两个存储器存储区域，以及形成覆盖所述至少两个存储器存储器 地区。 该装置可以用于例如VGA存储器阵列中。

公开(公告)号：US20060043482A1

公开(公告)日：2006-03-02

申请号：US10930891

申请日：2004-08-31

申请人： James Burnett ,  Gowrishankar Chindalore ,  Craig Swift ,  Ramachandran Muralidhar

发明人： James Burnett ,  Gowrishankar Chindalore ,  Craig Swift ,  Ramachandran Muralidhar

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/7881 ,  H01L29/7885

摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.