公开(公告)号：US20140203325A1

公开(公告)日：2014-07-24

申请号：US13747009

申请日：2013-01-22

申请人： Purakh Raj VERMA ,  Guowei ZHANG ,  Kah Wee ANG

发明人： Purakh Raj VERMA ,  Guowei ZHANG ,  Kah Wee ANG

IPC分类号： H01L21/02 ,  H01L31/028

CPC分类号： H01L21/02532 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/1203 ,  H01L31/028

摘要： A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.

摘要翻译： 提供了一种通过Ge或Ge / Si的非选择性外延生长在CMOS工艺中形成集成的Ge或Ge / Si光电检测器的方法和装置。 实施例包括在Si衬底中形成N阱; 在Si衬底中形成晶体管或电阻器; 在Si衬底和晶体管或电阻器上形成ILD; 在ILD上形成Si基电介质层; 在所述Si基电介质层上形成多晶硅或Si-Si层; 在多晶硅或a-Si层中形成沟槽，Si基介电层，ILD和N阱; 在沟槽中形成Ge或Ge / Si; 并且将Ge或Ge / Si，多晶硅或a-Si层以及Si基介电层除去到ILD的上表面。 另外的方面包括在Ge或Ge / Si上形成原位掺杂的Si帽外延层或非原位掺杂的多晶Si或者a-Si覆盖层。

公开(公告)号：US20130181287A1

公开(公告)日：2013-07-18

申请号：US13598605

申请日：2012-08-29

申请人： Guowei ZHANG ,  Purakh Raj VERMA

发明人： Guowei ZHANG ,  Purakh Raj VERMA

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28211 ,  H01L21/2822 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7816

摘要： A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion.

摘要翻译： 公开了一种形成装置的方法。 提供具有器件区域的衬底。 器件区域包括限定在其上的源极区域，栅极和漏极区域。 在与栅极的第二侧相邻的衬底中形成漂移阱。 漂移阱使栅极的一部分与栅极下方的漂移阱的第一边缘重叠。 在漂移井中形成次级部分。 次级部分使栅极的一部分与第二部分的栅极下方的第一边缘重叠。 次级部分的第一边缘偏离漂移井的第一边缘。 栅极的栅极电介质包括具有第一厚度的第一部分和具有第二厚度的第二部分。 第二部分在次级部分之上。

公开(公告)号：US07951680B2

公开(公告)日：2011-05-31

申请号：US12262120

申请日：2008-10-30

申请人： Guowei Zhang ,  Yisuo Li ,  Ming Li ,  Purakh Raj Verma ,  Shao-fu Sanford Chu

发明人： Guowei Zhang ,  Yisuo Li ,  Ming Li ,  Purakh Raj Verma ,  Shao-fu Sanford Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/66659 ,  H01L29/7834

摘要： A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.

摘要翻译： 一种用于制造集成电路系统的方法，包括：提供包括有源器件的衬底; 在所述衬底中形成漂移区域，所述漂移区域部分地由所述衬底的顶表面限定并与源极隔开; 并在漂移区上方形成漏极。

公开(公告)号：US20070054464A1

公开(公告)日：2007-03-08

申请号：US11222482

申请日：2005-09-08

申请人： Guowei Zhang

发明人： Guowei Zhang

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： An integrated circuit device having deeper STI trenches for device isolation and shallower STI trenches at the gate edge for low on-resistance and a method for forming the same are described. The integrated circuit device of the invention comprises a gate electrode on a gate dielectric layer overlying a substrate, source and drain regions within the substrate on either side of the gate, first dielectric trenches isolating the gate electrode and source and drain regions from other devices, and a second dielectric trench underlying an edge of the gate adjacent to the drain region wherein the second dielectric trench is shallower than the first dielectric trenches.

摘要翻译： 描述了具有用于器件隔离的较深STI沟槽和用于低导通电阻的栅极边缘处的较浅STI沟槽的集成电路器件及其形成方法。 本发明的集成电路器件包括位于衬底上的栅介质层上的栅电极，位于栅极两侧的衬底内的源极和漏极区域，将栅极电极和源极和漏极区域与其它器件隔离的第一介电沟槽， 以及第二电介质沟槽，其位于与漏极区相邻的栅极的边缘下方，其中第二电介质沟槽比第一电介质沟槽浅。

公开(公告)号：US20140264576A1

公开(公告)日：2014-09-18

申请号：US13832682

申请日：2013-03-15

申请人： Guowei ZHANG ,  Deyan CHEN

发明人： Guowei ZHANG ,  Deyan CHEN

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7817 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for forming a low Rdson LDNMOS and a high sheet resistance poly resistor and the resulting device are provided. Embodiments include forming first, second, and third STI regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with the first mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a second mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the second mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.

摘要翻译： 提供了用于形成低Rdson LDNMOS和高电阻聚电阻器的方法以及所得到的器件。 实施例包括在衬底中形成第一，第二和第三STI区域; 用第一掩模在第一STI区周围的衬底中形成P阱; 在具有第一掩模的P阱和第三STI区之间的衬底中形成N漂移区; 在所述衬底上形成介电层; 在所述电介质层上形成多晶硅层; 在第二和第三STI区域之间用第二掩模执行N-漏极注入; 在所述第二掩模中对所述多晶硅层进行电阻调整注入，但不通过所述多晶硅层; 以及在执行所述电阻调节注入之后构图所述多晶硅和电介质层以形成栅极堆叠和多晶硅电阻器，所述多晶硅电阻器形成在所述第三STI区域上并且与所述栅极叠层横向分离。

公开(公告)号：US08802484B1

公开(公告)日：2014-08-12

申请号：US13747009

申请日：2013-01-22

申请人： Purakh Raj Verma ,  Guowei Zhang ,  Kah Wee Ang

发明人： Purakh Raj Verma ,  Guowei Zhang ,  Kah Wee Ang

IPC分类号： H01L21/00 ,  H01L31/102

CPC分类号： H01L21/02532 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/1203 ,  H01L31/028

摘要： A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.

摘要翻译： 提供了一种通过Ge或Ge / Si的非选择性外延生长在CMOS工艺中形成集成的Ge或Ge / Si光电检测器的方法和装置。 实施例包括在Si衬底中形成N阱; 在Si衬底中形成晶体管或电阻器; 在Si衬底和晶体管或电阻器上形成ILD; 在ILD上形成Si基电介质层; 在所述Si基电介质层上形成多晶硅或Si-Si层; 在多晶硅或a-Si层中形成沟槽，Si基介电层，ILD和N阱; 在沟槽中形成Ge或Ge / Si; 并且将Ge或Ge / Si，多晶硅或a-Si层以及Si基介电层除去到ILD的上表面。 另外的方面包括在Ge或Ge / Si上形成原位掺杂的Si帽外延层或非原位掺杂的多晶Si或者a-Si覆盖层。

公开(公告)号：US20140048874A1

公开(公告)日：2014-02-20

申请号：US13587059

申请日：2012-08-16

申请人： Guowei ZHANG ,  Purakh Raj VERMA ,  Zhiqing LI

发明人： Guowei ZHANG ,  Purakh Raj VERMA ,  Zhiqing LI

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7835

摘要： LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.

摘要翻译： 在具有减小厚度的多晶硅层和源极/漏极结的器件中，LDD区域具有高的注入能量。 实施例包括在衬底表面上形成氧化物层，在氧化物层上形成多晶硅层，通过氧化物层和多晶硅层并在衬底表面之下形成第一和第二沟槽，在衬底表面之下限定栅极区域，注入掺杂剂 在通过第一和第二沟槽的LDD区域中，在栅极区域的相对侧表面上形成间隔物并且延伸到第一和第二沟槽中，并且在第一和第二沟槽中的每一个下方的源极/漏极区域中注入掺杂剂。

公开(公告)号：US20140042499A1

公开(公告)日：2014-02-13

申请号：US13569190

申请日：2012-08-08

申请人： Guowei ZHANG ,  Purakh Raj VERMA

发明人： Guowei ZHANG ,  Purakh Raj VERMA

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0638 ,  H01L21/76224 ,  H01L29/0603 ,  H01L29/0615 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench.

摘要翻译： 公开了一种形成装置的方法。 提供具有器件区域的衬底。 器件区域包括限定在其上的源极区域，栅极区域和漏极区域。 在栅极区域形成栅极，在源极区域形成源极，在漏极区域形成漏极。 在器件区域中的隔离区域中形成沟槽。 隔离区域使栅极的一部分成为底部。 在衬底上形成蚀刻停止（ES）应力层。 ES应力层对沟槽进行排列。

公开(公告)号：US08507983B2

公开(公告)日：2013-08-13

申请号：US13550571

申请日：2012-07-16

申请人： Guowei Zhang ,  Purakh Raj Verma

发明人： Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included.

摘要翻译： 公开了一种设备。 该器件包括用有源器件区域制备的衬底。 有源器件区域包括栅极。 该器件还包括在栅极的第一边缘附近设置在衬底中的掺杂沟道。 栅极的第一边缘与沟道的沟道边缘很好地与沟道的沟道边缘重叠。 栅极和沟道边缘的第一个边缘定义了器件的有效沟道长度。 有效通道长度与栅极自对准。 还包括与栅极的第二边缘相邻的掺杂漂移阱。

公开(公告)号：US20130181286A1

公开(公告)日：2013-07-18

申请号：US13352248

申请日：2012-01-17

申请人： Guowei ZHANG

发明人： Guowei ZHANG

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate.