公开(公告)号：US20100202209A1

公开(公告)日：2010-08-12

申请号：US12763127

申请日：2010-04-19

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C16/10

CPC classification number: G11C16/10

Abstract: A flash memory device includes a memory cell array on which data is stored, and page buffers that are connected to the memory cells through the bit lines and apply one of the first voltage, second voltage or third voltage between the first and second voltage, to the respective bit line when performing the program.

Abstract translation: 闪速存储器件包括存储有数据的存储单元阵列和通过位线连接到存储器单元并将第一和第二电压之间的第一电压，第二电压或第三电压中的一个施加到第一和第二电压之间的页缓冲器， 执行程序时的相应位线。

公开(公告)号：US07768833B2

公开(公告)日：2010-08-03

申请号：US12147109

申请日：2008-06-26

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04

CPC classification number: G11C16/3418

Abstract: A method of programming a non-volatile memory device includes, a bit line, to which a program-inhibited cell is connected, being precharged. After precharging the bit line, a program voltage is applied to a first word line selected for program. When a memory cell connected to a second word line, which is adjacent to the first word line in a direction of a drain select line, is a cell to be programmed, a first pass voltage is applied to the second word line and a second pass voltage is applied to the remaining word lines other than the first and second word lines.

Abstract translation: 对非易失性存储器件进行编程的方法包括被预充电的与程序禁止的单元连接的位线。 在对位线进行预充电之后，将程序电压施加到为程序选择的第一字线。 当连接到与排列选择线方向相邻的第一字线的第二字线的存储器单元是要被编程的单元时，第一通过电压被施加到第二字线并且第二通道 电压被施加到除第一和第二字线之外的剩余字线。

公开(公告)号：US07715238B2

公开(公告)日：2010-05-11

申请号：US12147165

申请日：2008-06-26

Applicant: Hee Youl Lee ,  Won Sic Woo

Inventor： Hee Youl Lee ,  Won Sic Woo

IPC: G11C11/00

CPC classification number: G11C16/34 ,  G11C16/10 ,  G11C16/3454

Abstract: An operation of a non-volatile memory device. A method of operating a non-volatile memory device in accordance with an aspect of the present invention, a first program operation is performed by applying a first program voltage to word lines of memory cells, constituting a memory block. As a result of the first program operation, threshold voltages of the memory cells are firstly measured. A second program operation is performed using a second program voltage, which is increased as much as a difference between a first threshold voltage, that is, a lowest voltage level of the firstly measured threshold voltages and a second threshold voltage, that is, an intermediate voltage level of the firstly measured threshold voltages. The second program operation is repeatedly performed by increasing the second program voltage as much as the difference between the first and second threshold voltages until the lowest threshold voltage becomes higher than a program verify voltage. A pass voltage is then set by reflecting a first voltage level, that is, a difference between a program voltage applied in a last program execution step and the first program voltage.

Abstract translation: 非易失性存储器件的操作。 根据本发明的一个方面的操作非易失性存储器件的方法，通过对构成存储器块的存储器单元的字线施加第一编程电压来执行第一编程操作。 作为第一编程操作的结果，首先测量存储单元的阈值电压。 使用第二编程电压执行第二编程操作，该第二编程电压被增加到第一阈值电压（即，首先测量的阈值电压的最低电压电平）与第二阈值电压之间的差，即中间 首先测量的阈值电压的电压电平。 通过将第二编程电压与第一和第二阈值电压之间的差异增加直到最低阈值电压变得高于编程验证电压来重复执行第二编程操作。 然后通过反映第一电压电平，即在最后程序执行步骤中施加的编程电压与第一编程电压之间的差异来设置通过电压。

公开(公告)号：US20100002520A1

公开(公告)日：2010-01-07

申请号：US12559374

申请日：2009-09-14

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass bias is applied to at least one of the memory cells in a source select line direction relative to the memory cell to which the program bias has been applied. A second pass bias is applied to the memory cells in a drain select line direction relative the memory cell(s) to which the first pass bias has been applied.

Abstract translation: 一种用于对闪速存储器件进行编程的方法包括将程序偏置应用于存储单元串内的多个存储单元的存储单元。 每个存储器单元串包括源选择线，多个存储单元和漏极选择线。 相对于已经应用了程序偏置的存储单元，在源选择线方向中的至少一个存储单元施加第一通过偏压。 相对于已经施加了第一通过偏压的存储单元，在漏选择线方向上对存储单元施加第二偏压。

公开(公告)号：US07602648B2

公开(公告)日：2009-10-13

申请号：US11843387

申请日：2007-08-22

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/3454

Abstract: A method for operating a flash memory device includes applying a first program voltage Vp1 to a plurality of word lines of memory cells. Threshold voltages of the memory cells are measured to obtain a first threshold voltage distribution for the memory cells. A second program voltage Vp2 is applied to the word lines of the memory cells that had been programmed with the first program voltage Vp1. The threshold voltages of the memory cells that have been programmed with the second program voltage Vp2 are measured to obtain a second threshold voltage distribution for the memory cells. A determination is made whether or not the memory cells that have been programmed with the second program voltage have been programmed properly. If the memory cells are determined to have been programmed properly, then the second program voltage is defined as an ending bias for a programming operation. If the memory cells are determined not to have been programmed properly, the memory cells are programmed using a third program voltage that is higher than the second program voltage.

Abstract translation: 一种用于操作闪速存储器件的方法包括将第一编程电压Vp1应用于存储器单元的多个字线。 测量存储器单元的阈值电压以获得存储单元的第一阈值电压分布。 第二编程电压Vp2被施加到已经用第一编程电压Vp1编程的存储器单元的字线。 测量已经用第二编程电压Vp2编程的存储单元的阈值电压，以获得存储单元的第二阈值电压分布。 确定已经用第二编程电压编程的存储单元是否已被正确编程。 如果确定存储器单元已被正确编程，则将第二编程电压定义为用于编程操作的结束偏置。 如果确定存储器单元未被正确编程，则使用高于第二编程电压的第三编程电压对存储器单元进行编程。

公开(公告)号：US20080123402A1

公开(公告)日：2008-05-29

申请号：US11618697

申请日：2006-12-29

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C7/00

CPC classification number: G11C16/0483

Abstract: A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass bias is applied to at least one of the memory cells in a source select line direction relative to the memory cell to which the program bias has been applied. A second pass bias is applied to the memory cells in a drain select line direction relative the memory cell(s) to which the first pass bias has been applied.

Abstract translation: 一种用于对闪速存储器件进行编程的方法包括将程序偏置应用于存储单元串内的多个存储单元的存储单元。 每个存储器单元串包括源选择线，多个存储单元和漏极选择线。 相对于已经应用了程序偏置的存储单元，在源选择线方向中的至少一个存储单元施加第一通过偏压。 相对于已经施加了第一通过偏压的存储单元，在漏选择线方向上对存储单元施加第二偏压。

公开(公告)号：US07142460B2

公开(公告)日：2006-11-28

申请号：US11158463

申请日：2005-06-21

Applicant: Hee Youl Lee ,  Sung Jae Chung

Inventor： Hee Youl Lee ,  Sung Jae Chung

IPC: G11C11/24

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/30

Abstract: A flash memory device has an improved pre-program function. The flash memory device comprises memory cell blocks each including wordlines, bitlines, and memory cells sharing common source lines; an erase controller generating a pre-program control signal in response to an erase command; and a voltage selection circuit selecting one of first and second common source voltages in response to one among the pre-program control signal, a read command, and a program command and outputting the selected voltage to a global common source line.

Abstract translation: 闪存设备具有改进的预编程功能。 闪存器件包括存储单元块，每个存储单元块包括字线，位线和共享公共源极线的存储器单元; 擦除控制器，其响应于擦除命令产生预编程控制信号; 以及电压选择电路，响应于所述预编程控制信号，读命令和编程命令中的一个选择第一和第二公共源电压中的一个，并将所选择的电压输出到全局公共源线。

公开(公告)号：US07035143B2

公开(公告)日：2006-04-25

申请号：US10876319

申请日：2004-06-24

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04 ,  G11C8/00 ,  G11C19/08

CPC classification number: G11C16/0483 ,  G11C16/24

Abstract: Provided is related to a NAND flash memory device and method of reading the same, in which during a read operation, a ground voltage is applied to string and ground selection transistors of deselected cell blocks so as to increase resistance of a string line to prevent leakage currents due to a back-bias effect. A reduced bitline leakage current increases an ON/OFF current ratio between programmed and erased cells to reduce a sensing time therein, which makes a read trip range so as to prevent variation of threshold voltages due to data retention and reading disturbance. Voltages can be independently applied to source selection lines by electrically isolating source selection transistors between the cell blocks. It is available to reduce the number of source discharge transistors by electrically connecting the source selection transistors between adjacent cell blocks.

Abstract translation: 本发明涉及一种NAND闪存器件及其读取方法，其中在读操作期间，将接地电压施加到取消选择的单元块的串和地选择晶体管，以增加串线的电阻以防止泄漏 由于偏置效应引起的电流。 减少的位线泄漏电流增加编程和擦除单元之间的ON / OFF电流比，以减少其中的感测时间，这使得读取跳闸范围，从而防止由于数据保持和读取干扰导致的阈值电压的变化。 可以通过电隔离单元块之间的源选择晶体管来独立地将电压施加到源选择线。 可以通过电连接相邻单元块之间的源极选择晶体管来减少源极放电晶体管的数量。

公开(公告)号：US06815283B2

公开(公告)日：2004-11-09

申请号：US10005843

申请日：2001-12-07

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: H01L218238

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534

Abstract: The present invention relates to a method of manufacturing a semiconductor device. The present invention sequentially forms a DCS HTO film and a nitride film on the entire structure after a self align source etch process so that so that they can serve as a spacer for compensating for the sidewall of a gate structure damaged upon the self align source etch process. Therefore, the present invention can increase the integrity capability of data by preventing movement of charges and holes between a floating gate electrode and peripheral circuits and can mitigate a stress due to the nitride film in a subsequent process. Further, the present invention can prevent increase of the thickness of the dielectric film between a first polysilicon silicon layer and a second polysilicon layer in a subsequent annealing process and can secure the uniformity of a screen oxide film to make uniform the depth of the junction upon a high concentration ion implantation process. In addition, the present invention can improve the characteristic of transistors in the peripheral circuit and improve the uniformity of the diffusion resistance value.

公开(公告)号：US5770502A

公开(公告)日：1998-06-23

申请号：US656446

申请日：1996-05-31

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: H01L21/265 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11517

Abstract: The present invention forms a modified DDD junction structure in which a DDD structure is formed on stack gate structure side on which a floating gate and a control gate are laminated and a non-DDD structure is formed on split gate side, by forming a first impurity region through a tilt angle implanting of impurity ions at a high level of energy and then forming a second impurity region through a tilt angle implanting of impurity ions at a low level of of energy using a spacer.

Abstract translation: 本发明形成了一种改进的DDD结结构，其中在层叠栅极结构侧上形成DDD结构，在栅极结构侧上层叠有浮动栅极和控制栅极，并且在分裂栅极侧上形成非DDD结构，通过形成第一杂质 通过以高能量注入杂质离子的倾斜角，然后通过使用间隔物以低水平的能量注入杂质离子的倾斜角形成第二杂质区域。