公开(公告)号：US5600155A

公开(公告)日：1997-02-04

申请号：US572357

申请日：1995-12-14

申请人： I-Wei Wu

发明人： I-Wei Wu

IPC分类号： G02F1/136 ,  G02F1/1368 ,  H01L23/482 ,  H01L23/532 ,  H01L23/538 ,  H01L29/04 ,  G02F1/1343

CPC分类号： H01L23/4825 ,  H01L23/53257 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Array circuitry formed at the surface of a substrate includes M scan lines that cross N data lines. The array circuitry also includes cell circuitry connected to the mth scan line and the nth data line. The cell circuitry includes a component with a data lead for receiving signals from or providing signals to the nth data line. The cell circuitry also includes connecting circuitry with first and second semiconductor lines. The first semiconductor line has a channel between the nth data line and the data lead of the component. The second semiconductor line is connected to the mth scan line and crosses the first semiconductor line at the channel. Because the second semiconductor line is conductive, signals on the mth scan line control conductivity of the channel. The semiconductor lines can be polysilicon, and the scan lines can be aluminum. The component can include a capacitive element with one electrode under the (m+1)th scan line, part of which forms the other electrode of the capacitor. The channel can be under the nth data line, leaving the cell area free. The component can also include a light transmissive cell electrode in the cell area, and the array circuitry can be used in a display, with liquid crystal material positioned along the cell electrode. The display can also include peripheral circuitry outside the boundary of the array circuitry, connected to the scan lines and data lines.

摘要翻译： 形成在衬底表面的阵列电路包括跨越N条数据线的M条扫描线。 阵列电路还包括连接到第m条扫描线和第n条数据线的单元电路。 单元电路包括具有用于从第n个数据线接收信号或向第n个数据线提供信号的数据引线的部件。 单元电路还包括具有第一和第二半导体线路的连接电路。 第一半导体线具有在第n个数据线和部件的数据引线之间的通道。 第二半导体线路连接到第m条扫描线，并且在通道处与第一半导体线路交叉。 由于第二半导体线路是导通的，所以第m条扫描线上的信号控制通道的电导率。 半导体线可以是多晶硅，扫描线可以是铝。 该元件可以包括在第（m + 1）扫描线下方的一个电极的电容元件，其中的一部分形成电容器的另一个电极。 通道可以在第n条数据线之下，使单元区域空闲。 该组件还可以在单​​元区域中包括透光单元电极，阵列电路可用于显示器，液晶材料沿着单元电极定位。 显示器还可以包括连接到扫描线和数据线的阵列电路边界之外的外围电路。

公开(公告)号：US07480020B2

公开(公告)日：2009-01-20

申请号：US10942683

申请日：2004-09-16

申请人： Chi-Jain Wen ,  Dai-Liang Ting ,  Gwo-long Lin ,  Shyuan-Jeng Ho ,  I-Wei Wu

发明人： Chi-Jain Wen ,  Dai-Liang Ting ,  Gwo-long Lin ,  Shyuan-Jeng Ho ,  I-Wei Wu

IPC分类号： G02F1/1335

CPC分类号： G02F1/133555 ,  G02F1/13439

摘要： A transflective liquid crystal display and method of fabricating the same. The pixel region of the transflective comprises a thin film transistor, a transmissive electrode, and a reflective electrode, wherein the overlap of the reflective electrode and the transparent electrode composes a reflective region and the non-overlapping region of the reflective electrode and the transparent electrode form a transmissive region, and the transparent electrode and the source and the drain regions of the thin film transistor are formed of the same silicon layer.

摘要翻译： 半透射型液晶显示器及其制造方法。 半透反射体的像素区域包括薄膜晶体管，透射电极和反射电极，其中反射电极和透明电极的重叠构成反射区域和反射电极与透明电极的非重叠区域 形成透射区域，并且薄膜晶体管的透明电极和源极和漏极区域由相同的硅层形成。

公开(公告)号：US20050213002A1

公开(公告)日：2005-09-29

申请号：US10942683

申请日：2004-09-16

申请人： Chi-Jain Wen ,  Dai-Liang Ting ,  Gwo-Iong Lin ,  Shyuan-Jeng Ho ,  I-Wei Wu

发明人： Chi-Jain Wen ,  Dai-Liang Ting ,  Gwo-Iong Lin ,  Shyuan-Jeng Ho ,  I-Wei Wu

IPC分类号： G02F1/1335 ,  G02F1/1343

CPC分类号： G02F1/133555 ,  G02F1/13439

摘要： A transflective liquid crystal display and method of fabricating the same. The pixel region of the transflective comprises a thin film transistor, a transmissive electrode, and a reflective electrode, wherein the overlap of the reflective electrode and the transparent electrode composes a reflective region and the non-overlapping region of the reflective electrode and the transparent electrode form a transmissive region, and the transparent electrode and the source and the drain regions of the thin film transistor are formed of the same silicon layer.

摘要翻译： 半透射型液晶显示器及其制造方法。 半透反射体的像素区域包括薄膜晶体管，透射电极和反射电极，其中反射电极和透明电极的重叠构成反射区域和反射电极与透明电极的非重叠区域 形成透射区域，并且薄膜晶体管的透明电极和源极和漏极区域由相同的硅层形成。

公开(公告)号：US5557534A

公开(公告)日：1996-09-17

申请号：US367983

申请日：1995-01-03

申请人： I-Wei Wu

发明人： I-Wei Wu

IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/768 ,  H01L23/482 ,  H01L23/52 ,  H01L23/532 ,  H01L23/538 ,  H01L27/12 ,  H01L29/786 ,  H01L21/72

CPC分类号： H01L23/4825 ,  H01L21/768 ,  H01L23/53257 ,  H01L23/5386 ,  G02F1/1362 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Array circuitry formed at a surface of a substrate includes a first conductive layer with M scan lines, a second conductive layer with N data lines, and cell circuitry for a region in which the mth scan line and the nth data line cross. The cell circuitry includes a component with a data lead for receiving signals from or providing signals to the nth data line. A first semiconductor layer of the cell circuitry includes a first line with a channel between a connecting point to the nth data line and a connecting point to the component's data lead. A second semiconductor layer includes a second line extending from a connecting point to the mth scan line and crossing the first line at the channel. The first and second conductive layers and the cell circuitry are formed with electrical connections at the connecting points so that signals on the mth scan line control conductivity of the first line between the nth data line and the data lead. The semiconductor layers can be polysilicon. The first semiconductor layer can be formed before the second, with the first line electrically connected to the data lead by implanting a dopant. The connections to the mth scan line and the nth data line can be metal/semiconductor interfaces, with the first conductive layer deposited on the second line and with the second conductive layer deposited on the first line through an opening in an insulating layer.

摘要翻译： 形成在衬底的表面上的阵列电路包括具有M条扫描线的第一导电层，具有N条数据线的第二导电层和用于第m条扫描线和第n条数据线交叉的区域的单元电路。 单元电路包括具有用于从第n个数据线接收信号或向第n个数据线提供信号的数据引线的部件。 单元电路的第一半导体层包括具有在连接到第n数据线的连接点和与部件的数据引线的连接点之间的通道的第一线。 第二半导体层包括从连接点延伸到第m条扫描线并与通道上的第一条线交叉的第二条线。 第一和第二导电层和单元电路在连接点处形成有电连接，使得第m条扫描线上的信号控制第n条数据线和数据引线之间的第一条线的电导率。 半导体层可以是多晶硅。 第一半导体层可以在第二半导体层之前形成，其中第一线通过注入掺杂剂与数据引线电连接。 与第m扫描线和第n数据线的连接可以是金属/半导体接口，其中第一导电层沉积在第二线上，并且第二导电层通过绝缘层中的开口沉积在第一线上。

公开(公告)号：US4988638A

公开(公告)日：1991-01-29

申请号：US546288

申请日：1990-06-29

申请人： Tiao-Yuan Huang ,  Anne Chiang ,  I-Wei Wu

发明人： Tiao-Yuan Huang ,  Anne Chiang ,  I-Wei Wu

IPC分类号： H01L27/092 ,  H01L29/786

CPC分类号： H01L27/1251 ,  H01L27/092 ,  H01L27/1214 ,  H01L29/78663 ,  H01L29/78672

摘要： A thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

摘要翻译： 一种薄膜SOI CMOS器件，其中同时沉积n沟道晶体管和p沟道晶体管的适当掺杂的沉积层。 一个晶体管的源极和漏极元件和另一个晶体管的栅极元件形成在下部，高度掺杂的半导体层中，并且与相应的栅极元件分离，并且源极和漏极元件形成在上部，高度掺杂的半导体层 。 层级由夹持介电层的两个本征或轻掺杂半导体层分开，使得邻近源极和漏极元件的本征或轻掺杂半导体层用作有源沟道层，并且本征或轻掺杂半导体层位于 邻接于栅极元件用于延伸栅极层。

公开(公告)号：US4904611A

公开(公告)日：1990-02-27

申请号：US277432

申请日：1988-11-25

申请人： Anne Chiang ,  I-Wei Wu ,  Tiao-Yuan Huang

发明人： Anne Chiang ,  I-Wei Wu ,  Tiao-Yuan Huang

IPC分类号： H01L21/20

CPC分类号： H01L21/2022 ,  Y10S148/132

摘要： A method of forming large grain polycrystalline films by deep ion implantation into a composite structure, comprising a layer of amorphous semiconductor material upon an insulating substrate. Implantation is of a given ion species at an implant energy and dosage sufficient to distrupt the interface between the amorphous layer and the substrate and to retard the process of nucleation in subsequent random crystallization upon thermal annealing.

摘要翻译： 通过深离子注入将大晶粒多晶膜形成复合结构的方法，其包括在绝缘基板上的非晶半导体材料层。 植入是一种给定的离子种类，其植入能量和剂量足以破坏非晶层和基底之间的界面，并且在热退火后的随后随机结晶中阻止成核过程。