公开(公告)号：US5338700A

公开(公告)日：1994-08-16

申请号：US47668

申请日：1993-04-14

申请人： Charles H. Dennison ,  Aftab Ahmad

发明人： Charles H. Dennison ,  Aftab Ahmad

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/72

CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90

摘要： A method of forming a bit line over capacitor array of memory cells includes providing first conductive material pillars within first contact openings downwardly to active (source/drain) areas for ultimate connection with bit lines. A covering layer of insulating material is provided over the first pillars, and contact openings provided therethrough to electrically connect with other active (source/drain) areas for formation of capacitors. Capacitors are then provided within the capacitor contact openings. An overlying layer of insulating material is then provided over the covering layer of insulating material and over the capacitors. Bit line contact openings are then provided through the overlying layer and the covering layer to the first pillar upper surfaces. Then, a digit line layer of conductive material is provided atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

摘要翻译： 在存储器单元的电容器阵列上形成位线的方法包括：将第一接触开口内的第一导电材料柱向下提供到用于与位线最终连接的有源（源极/漏极）区域。 绝缘材料的覆盖层设置在第一柱上，并且穿过其设置的接触开口与其他有源（源极/漏极）区域电连接以形成电容器。 然后在电容器接触开口内提供电容器。 然后在绝缘材料的覆盖层上和电容器上方覆盖绝缘材料层。 然后将位线接触开口穿过覆盖层和覆盖层提供到第一柱上表面。 然后，导电材料的数字线层被提供在晶片顶部和位线接触开口内，数字线层与第一柱上表面电连接。

公开(公告)号：US5266511A

公开(公告)日：1993-11-30

申请号：US954032

申请日：1992-09-30

申请人： Yoshihiro Takao

发明人： Yoshihiro Takao

IPC分类号： H01L21/304 ,  H01L21/762 ,  H01L21/764 ,  H01L21/822 ,  H01L21/98 ,  H01L23/544 ,  H01L21/72

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/76251 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S438/975

摘要： A first semiconductor substrate comprises an integrated circuit formed therein and an alignment mark formed thereon. The top surface of the first semiconductor substrate is covered with a first insulating layer and is planarized. The alignment mark is formed in a space between a plurality of groups of elements, such as a scribe line area. A second semiconductor substrate is provided with a groove corresponding to said space, or scribe line area, and a second insulating layer is formed on thereon and so as to bury the groove, and the exposed surface of the second insulating layer is planarized. The two planarized surfaces of the first and second semiconductor substrates are positioned in facing, contiguous relationship and are bonded to each other, while an infra-red microscope is used for alignment of the space and the groove. The back surface of the second semiconductor substrate is selectively etched until the second insulating layer, as filed in the groove, is exposed. A second integrated circuit is formed in the second semiconductor substrate at a position therein determined by detecting the alignment mark on the first semiconductor substrate through a visible ray microscope.

摘要翻译： 第一半导体衬底包括形成在其中的集成电路和形成在其上的对准标记。 第一半导体衬底的顶表面被第一绝缘层覆盖并被平坦化。 对准标记形成在诸如划线区域的多组元件之间的空间中。 第二半导体衬底设置有对应于所述空间或划线区域的凹槽，并且在其上形成第二绝缘层，以便掩埋沟槽，并且使第二绝缘层的暴露表面平坦化。 第一和第二半导体衬底的两个平坦化表面以面对的连续关系定位并且彼此结合，而使用红外显微镜来对准空间和沟槽。 选择性地蚀刻第二半导体衬底的背面，直到露出凹槽中的第二绝缘层为止。 第二集成电路通过可见光显微镜检测在第一半导体衬底上的对准标记确定的位置处形成在第二半导体衬底中。

公开(公告)号：US4559696A

公开(公告)日：1985-12-24

申请号：US629576

申请日：1984-07-11

申请人： Kranti Anand ,  Robert J. Strain

发明人： Kranti Anand ,  Robert J. Strain

IPC分类号： H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/167 ,  H01L29/737 ,  H01L29/161 ,  H01L21/72

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L29/167 ,  H01L29/7375

摘要： The suppression of the reverse injection of the carriers in a bipolar transistor, without adversely effecting forward injection, is carried out by modifying the energy gap characteristics of the transistor so that a greater barrier to reverse injection is presented than that which is confronted by the forward injected carriers. The energy gap of the emitter is increased, relative to that of the base, through ion implantation. The ions which are implanted are such that the resulting compound material has a higher energy gap than that of silicon into which they are implanted to selectively modify the emitter region so as to locally increase its energy gap. Preferred materials include carbon and nitrogen.

摘要翻译： 通过改变晶体管的能隙特性来进行在双极晶体管中反向注入双极晶体管中的反向注入，而不会不利地影响正向注入，使得呈现比反向注入更大的阻碍 注射载体。 通过离子注入，发射极的能隙相对于基极的能隙增加。 所植入的离子使得所得到的化合物材料具有比它们被植入的硅更高的能隙，以选择性地修改发射区，从而局部增加其能隙。 优选的材料包括碳和氮。

公开(公告)号：US4082572A

公开(公告)日：1978-04-04

申请号：US721537

申请日：1976-09-08

申请人： Thomas R. Anthony ,  Harvey E. Cline

发明人： Thomas R. Anthony ,  Harvey E. Cline

IPC分类号： H01L21/24 ,  H01L21/74 ,  H01L23/48 ,  H01L27/08 ,  H01L27/10 ,  H01L29/8605 ,  H01L21/76 ,  H01L21/72

CPC分类号： H01L27/0802 ,  H01L21/24 ,  H01L21/743 ,  H01L23/481 ,  H01L27/101 ,  H01L29/8605 ,  H01L2924/0002 ,  H01L2924/15174 ,  Y10T29/49082 ,  Y10T29/49101

摘要： An anisotropic resistor for electrical feed throughs embodies a body of semiconductor material having at least one channel region of recrystallized material of the body formed therein. The channel region extends entirely through, and terminates in two major opposed surfaces of, the body. The at least one region is formed by a temperature gradient zone melting process, has a substantially uniform level of resistivity throughout the region and is electrically conductive.

公开(公告)号：US4079489A

公开(公告)日：1978-03-21

申请号：US755524

申请日：1976-12-30

申请人： John Lawrence Kowalski ,  Mark Joseph Michaels ,  Edmund Harold Schieve

发明人： John Lawrence Kowalski ,  Mark Joseph Michaels ,  Edmund Harold Schieve

IPC分类号： H01L21/50 ,  B23P19/04 ,  H01L21/00 ,  H01L21/60 ,  H01L21/68 ,  H01L21/70 ,  H05K13/04 ,  H01L21/72

CPC分类号： H01L24/75 ,  H01L21/67144 ,  H01L24/83 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/5149 ,  Y10T29/5191 ,  Y10T29/53178 ,  Y10T29/53191 ,  Y10T29/53478

摘要： A machine for blanking an integrated circuit chip from a segment of a film strip held in a fixture, forming its leads, and placing the chip on a multilayer substrate. The fixtures are stacked in a magazine which is mounted on the machine. A transfer mechanism transfers one fixture at a time from the magazine to a punch press where the IC chip is blanked from its film segment, and its leads are formed. The punch is retracted, and a multilayer substrate, which is mounted on an X-Y table, is positioned by the table under the punch so that the excised chip is directly above a chip pad and the chip leads are above the chip lead pads of a predetermined chip pad. The punch is lowered to position the chip on its chip pad. The substrate is coated with an adhesive flux to retain the chips and their leads in place. The punch is retracted and the X-Y table is moved to clear the punch press. A microcomputer controls the machine.

摘要翻译： 一种用于从保持在夹具中的胶片条的片段冲裁集成电路芯片的机器，形成其引线，并将芯片放置在多层基板上。 夹具堆叠在安装在机器上的盒子中。 一个传送机构一次将一个夹具从盒子传送到冲压机，其中IC芯片从其膜段中冲裁，并且其引线形成。 将冲头缩回，并且安装在XY工作台上的多层基板通过工作台在冲头下方定位，使得切除的芯片直接在芯片焊盘的上方，并且芯片引线位于预定的芯片引线板上方 芯片垫 将冲头降低以将芯片定位在其芯片垫上。 用粘合剂焊剂涂覆基材以将芯片及其引线保持在适当位置。 冲压机被收回，X-Y工作台移动以清除冲压机。 微机控制机器。

公开(公告)号：US5371033A

公开(公告)日：1994-12-06

申请号：US194498

申请日：1994-02-10

申请人： Seo K. Lee ,  Uja Shinji

发明人： Seo K. Lee ,  Uja Shinji

IPC分类号： H01L27/148 ,  H01L21/72 ,  H01L21/339

CPC分类号： H01L27/14887

摘要： A CCD image sensor comprising: a semiconductor substrate of a first conductivity type connected to a ground; an impurity region of a second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type, to serve as a blooming prevention layer; an impurity region of the first conductivity type formed in the surface of the semiconductor substrate, so that it encloses the impurity region of the second conductivity type serving as a blooming prevention layer, to serve as a potential barrier layer; an impurity region of the second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type so that it encloses the impurity region of the first conductivity type serving as a potential barrier layer, to serve as a light receiving region; an insulation film which is formed on the surface of the semiconductor substrate of the first conductivity type and has contact holes at both edges of the impurity region of the second conductivity type, serving as a blooming prevention layer; silicide films filled in the contact holes; and a light shield conductor film which is formed on the surface of the remaining insulation film, except for a portion between the silicide films and the surfaces of the silicide films, and is connected to a voltage source.

摘要翻译： 一种CCD图像传感器，包括：连接到地面的第一导电类型的半导体衬底; 形成在第一导电类型的半导体衬底的表面中的第二导电类型的杂质区域用作防起霜层; 形成在半导体衬底的表面中的第一导电类型的杂质区，使得其包围用作防止遮光层的第二导电类型的杂质区，用作势垒层; 形成在第一导电类型的半导体衬底的表面中的第二导电类型的杂质区域，使得其包围用作势垒层的第一导电类型的杂质区域用作光接收区域; 绝缘膜，其形成在第一导电类型的半导体衬底的表面上，并且在第二导电类型的杂质区的两个边缘处具有接触孔，用作防起霜层; 填充在接触孔中的硅化物膜; 以及形成在剩余绝缘膜的表面上的除了硅化物膜与硅化物膜的表面之间的部分之外的光屏蔽导体膜，并且连接到电压源。

公开(公告)号：US5364801A

公开(公告)日：1994-11-15

申请号：US65694

申请日：1993-05-21

申请人： Michael C. Smayling ,  Luciano Talamonti

发明人： Michael C. Smayling ,  Luciano Talamonti

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H02M3/07 ,  H01L21/72

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H02M3/073

摘要： A charge pump (10) uses Schottky diodes (12) coupled to clock signals (.phi..sub.1 and .phi..sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

摘要翻译： 电荷泵（10）使用通过相应电容器（14a-d）耦合到时钟信号（phi 1和phi 2）的肖特基二极管（12）。 调节和控制电路18提供稳定的电压输出并控制时钟电路（16）。

公开(公告)号：US5294561A

公开(公告)日：1994-03-15

申请号：US011460

申请日：1993-08-25

申请人： Takaho Tanigawa

发明人： Takaho Tanigawa

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/72

CPC分类号： H01L27/10852 ,  H01L21/76802 ,  H01L28/40

摘要： An impurity doped region is formed in a semiconductor substrate, and an insulating layer is formed thereon. A conductive layer is formed and is patterned by a photolithography process Then, a conductive sidewall is formed inside of the conductive layer. The insulating layer is etched with a mask of the conductive sidewall and the conductive layer to create a contact hole leading to the impurity doped region. A capacitor lower electrode layer is deposited within the contact hole. Thus, a capacitor insulating layer and a capacitor upper electrode layer are formed, to obtain a stacked capacitor.

摘要翻译： 在半导体衬底中形成杂质掺杂区，并在其上形成绝缘层。 形成导电层并通过光刻工艺图案化。然后，在导电层的内部形成导电侧壁。 用导电侧壁和导电层的掩模蚀刻绝缘层，以产生通向杂质掺杂区的接触孔。 电容器下电极层沉积在接触孔内。 因此，形成电容器绝缘层和电容器上电极层，以获得叠层电容器。

公开(公告)号：US4694561A

公开(公告)日：1987-09-22

申请号：US676677

申请日：1984-11-30

申请人： Joseph Lebowitz ,  William T. Lynch

发明人： Joseph Lebowitz ,  William T. Lynch

IPC分类号： H01L27/04 ,  G11C11/34 ,  G11C11/403 ,  H01L21/225 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/72 ,  H01L21/385

CPC分类号： H01L27/10861 ,  H01L21/2257 ,  H01L29/945 ,  Y10S148/109

摘要： A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a modified version of the doping technique described in U.S. Pat. No. 4,471,524 and 4,472,212. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.

摘要翻译： 用于动态随机存取存储器（DRAM）单元的高电容（Hi-C）电容器的沟槽版本是利用美国专利No. 第4,471,524和4,472,212号。 由此形成浅的高掺杂沟槽区域。 同时，结构的选定的侧表面部分也因此被高度掺杂。 这些表面部分允许容易地在电容器和随后形成的相邻存取晶体管之间进行直接电连接。

公开(公告)号：US4440580A

公开(公告)日：1984-04-03

申请号：US364156

申请日：1982-03-31

申请人： Hans-Juergen Gahle

发明人： Hans-Juergen Gahle

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/265 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L21/223 ,  H01L21/72

CPC分类号： H01L21/033 ,  H01L21/2652

摘要： The invention relates to an ion-implantation process for fabricating integrated bipolar planar transistors, particularly transistors for very high frequencies. To prevent the variations in the thicknesss of the insulating layer, through which the dopants for the base region are implanted into the semiconductor body in the form of ions, from causing variations in current gain, the dopants for the emitter regions are implanted through the same insulating layer as the dopants for the base region. The total charge in the base region below the emitter region thus becomes substantially independent of thickness variations of the insulating layer through which the dopants for the emitter region and those for the base region are implanted.

摘要翻译： 本发明涉及用于制造集成双极平面晶体管，特别是用于非常高频率的晶体管的离子注入工艺。 为了防止基极区域的掺杂剂以离子的形式注入到半导体本体中的绝缘层的厚度的变化引起电流增益的变化，发射极区域的掺杂剂通过相同的方式被注入 绝缘层作为基极区域的掺杂剂。 因此，在发射极区域之下的基极区域中的总电荷基本上不依赖于注入发射极区域和基极区域的掺杂剂的绝缘层的厚度变化。