公开(公告)号：US20050158938A1

公开(公告)日：2005-07-21

申请号：US10761658

申请日：2004-01-20

Applicant: Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0921 ,  H01L21/823892 ,  H01L27/0928

Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

Abstract translation: CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱，每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中，其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。

公开(公告)号：US20050110095A1

公开(公告)日：2005-05-26

申请号：US10718363

申请日：2003-11-20

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC: H01L21/331 ,  H01L23/62 ,  H01L27/02 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L27/0255

Abstract: The invention describes structures and a process for providing ESD protection between multiple power supply lines or buses on an integrated circuit chip. Special diode strings are used for the protection devices whereby the diodes are constructed across the boundary of an N-well and P substrate or P-well. The unique design provides very low leakage characteristics during normal circuit operation, as well as improved trigger voltage control achieved by stacking 2 or more diodes in a series string between the power buses.

Abstract translation: 本发明描述了在集成电路芯片上的多个电源线或总线之间提供ESD保护的结构和过程。 专用二极管串用于保护装置，由此二极管跨越N阱和P衬底或P阱的边界构造。 独特的设计在正常电路操作期间提供非常低的泄漏特性，以及通过在电源总线之间串联串联的2个或更多个二极管来实现的改进的触发电压控制。

公开(公告)号：US06888248B2

公开(公告)日：2005-05-03

申请号：US10401090

申请日：2003-03-26

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Jiaw-Ren Shih

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Jiaw-Ren Shih

IPC: H01L23/60 ,  H01L27/02 ,  H01L23/48

CPC classification number: H01L27/0288 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.

Abstract translation: 公开了一种多级金属互连结构及其形成方法，用于改善CMOS晶体管对静电放电（ESD）瞬变事件的电阻。 一种半导体器件，包括至少一个NMOS晶体管，沿着至少一个电路通路电连接到输入/输出信号源和参考电压电位; 并且至少通过将金属互连线长度部分的至少一部分压缩成在所述金属互连线长度部分的预定体积内的蛇形形状，将至少一个所述输入/输出信号源电连接至所述至少一个NMOS晶体管， 半导体器件。

公开(公告)号：US20050088801A1

公开(公告)日：2005-04-28

申请号：US10694129

申请日：2003-10-27

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01G4/228 ,  H01G4/35 ,  H01L21/8234 ,  H01L23/60 ,  H02H9/00

CPC classification number: H01L27/0251

Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

Abstract translation: 在集成电路（IC）上提供了具有增加的静电放电阻抗（ESD）的去耦电容器。 电容器可以是单指或多指。 在一个示例中，电容器包括由电介质材料隔开的第一和第二电极，靠近第一电极定位的源，以及靠近第一电极定位并与第一电极分离的浮动漏极。 通过源极，浮置漏极和掺杂区域之间的电流相互作用形成了被建模为双极结型晶体管（BJT）的寄生元件。 浮动漏极在BJT的基极处提供恒定的电位区域，从而最大程度降低对IC的ESD损坏。

公开(公告)号：US20050082618A1

公开(公告)日：2005-04-21

申请号：US10929735

申请日：2004-08-30

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0266

Abstract: A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

公开(公告)号：US06876041B2

公开(公告)日：2005-04-05

申请号：US09974056

申请日：2001-10-11

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0266 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides an ESD protection component, comprising at least two MOS field effect transistors (FETs) of a first conductivity type and a first well having a first conductivity type. The two MOS FETs have two parallel gates formed on a first semiconductive layer having a second conductivity type. The first well formed on the first semiconductive layer is comprised of a connecting area formed between the MOS FETs, two parallel extension areas formed perpendicular to the gates of the MOS FETs, and a first doping area of the second conductivity type formed in the connecting area. Two SCR are formed with drains of the MOS FETs, the first semiconductive layer, the first well and the first doping region. With the combination of the SCR and NMOS FET, ESD protection efficiency can be substantially enhanced.

Abstract translation: 本发明提供一种ESD保护元件，包括至少两个具有第一导电类型的MOS场效应晶体管（FET）和具有第一导电类型的第一阱。 两个MOS FET具有形成在具有第二导电类型的第一半导体层上的两个平行栅极。 形成在第一半导体层上的第一阱包括形成在MOS FET之间的连接区域，垂直于MOS FET的栅极形成的两个平行延伸区域和形成在连接区域中的第二导电类型的第一掺杂区域 。 两个SCR形成有MOS FET的漏极，第一半导体层，第一阱和第一掺杂区。 通过SCR和NMOS FET的组合，可以显着提高ESD保护效率。

公开(公告)号：US20050057872A1

公开(公告)日：2005-03-17

申请号：US10661895

申请日：2003-09-11

Applicant: Jian-Hsing Lee ,  Yi-Hsun Wu

Inventor： Jian-Hsing Lee ,  Yi-Hsun Wu

IPC: H01L27/02 ,  H02H3/00

CPC classification number: H01L27/0251

Abstract: An integrated circuit voltage excursion protection apparatus and method are disclosed for sensing voltage excursions at points on the integrated circuit and utilizes the output drivers of the I/O section of the integrated circuit to dissipate charge from such events. The apparatus may be used alone or in conjunction with other conventional dissipation apparatus.

Abstract translation: 公开了用于感测集成电路上的点处的电压偏移的集成电路电压偏移保护装置和方法，并且利用集成电路的I / O部分的输出驱动器从这种事件中消耗电荷。 该装置可以单独使用或与其他常规的耗散装置结合使用。

公开(公告)号：US06762439B1

公开(公告)日：2004-07-13

申请号：US09898386

申请日：2001-07-05

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Ta-Lee Yu

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Ta-Lee Yu

IPC: H01L2974

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.

Abstract translation: 实现了新的静电放电保护装置。 p阱区位于半导体衬底中。 p阱区域中的n +区域连接到第一电压源。 p阱区域中的n阱区域与n +区域间隔开，使得在正常操作期间耗尽区域将在其间延伸。 在正常操作期间，n阱区域中的p +区域连接到比第一电压源更大的值的第二电压源。 在静电放电事件期间，电流通过n +区域传导到p +区域。

公开(公告)号：US06674622B1

公开(公告)日：2004-01-06

申请号：US10037579

申请日：2002-01-04

Applicant: Ta-Lee Yu ,  Jian-Hsing Lee

Inventor： Ta-Lee Yu ,  Jian-Hsing Lee

IPC: H02H322

CPC classification number: H01L27/0262 ,  H01L27/0266 ,  H01L29/7436

Abstract: This invention provides a circuit and a method for protecting electronic circuits from electrostatic damage ESD. The invention teaches a dynamic floating silicon-controlled rectifier SCR for use as an ESD clamp. The n-well of the SCR is biased to the supply voltage Vdd under normal conditions to provide good latch-up performance. During ESD events, the n-well is floated to improve clamping performance. In addition, this invention utilizes a floating-well control circuit which provides better latch-up immunity during normal operation after the ESD event has passed.

Abstract translation: 本发明提供一种用于保护电子电路免受静电损伤ESD的电路和方法。 本发明教导了用作ESD钳位的动态浮动硅控整流器SCR。 在正常条件下，SCR的n阱被偏置到电源电压Vdd以提供良好的闭锁性能。 在ESD事件期间，n阱浮起以提高夹紧性能。 此外，本发明利用浮动阱控制电路，其在ESD事件通过之后在正常操作期间提供更好的闭锁抑制。

公开(公告)号：US06611028B2

公开(公告)日：2003-08-26

申请号：US10266661

申请日：2002-10-08

Applicant: Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

Inventor： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.