公开(公告)号：US07649262B2

公开(公告)日：2010-01-19

申请号：US12537328

申请日：2009-08-07

申请人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

发明人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC分类号： H01L23/48

CPC分类号： H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

摘要翻译： 用于抑制半导体处理中的局部金属沉淀形成（LMPF）的结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US20090294968A1

公开(公告)日：2009-12-03

申请号：US12537328

申请日：2009-08-07

申请人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

发明人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC分类号： H01L23/532

CPC分类号： H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

摘要翻译： 用于抑制半导体处理中的局部金属沉淀形成（LMPF）的结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US20090158230A1

公开(公告)日：2009-06-18

申请号：US11955653

申请日：2007-12-13

申请人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

发明人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

摘要翻译： 公开了一种确定绝缘体上半导体（SOI）技术的允许天线极限的方法。 在一个实施例中，该方法可以包括：确定门上的天线面积; 确定源/漏极上的天线面积; 确定栅极和源极/漏极网之间的总栅极绝缘体面积; 并且计算作为网之间的总门绝缘体面积的函数的可允许天线面积，使得允许较大的总天线面积用于网之间较大的总栅极绝缘体面积。

公开(公告)号：US20090094567A1

公开(公告)日：2009-04-09

申请号：US11869176

申请日：2007-10-09

申请人： Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

发明人： Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/60 ,  H01L2223/6677 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such possibilities are based on the connection order, the size of the antennas, and the likelihood that charges will flow from the antennas through insulators of the devices. If a significant possibility for damage exists, the method can reduce the size of the antenna.

摘要翻译： 本文的方法实施例确定连接顺序，其中将连接有源器件连接到给定电路设计内的天线。 该方法还评估了这些与天线的连接在连接到天线的设备中将导致充电损坏的可能性。 这种可能性基于连接顺序，天线的尺寸以及电荷将从天线通过设备的绝缘体流过的可能性。 如果存在损坏的重大可能性，则该方法可以减小天线的尺寸。

公开(公告)号：US07232695B2

公开(公告)日：2007-06-19

申请号：US11160154

申请日：2005-06-10

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC分类号： G01R31/26

CPC分类号： H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.

摘要翻译： 一种用于确定包含集成电路的晶片的最终导电互连上的钝化材料的完全覆盖的方法和装置。 在集成电路的制造期间形成具有集成电路的最终互连尺寸的测试结构，并且用于通过在测试结构处在钝化材料中形成开口来确定晶片的完全覆盖，开口的尺寸为 指示晶片的完全覆盖。

公开(公告)号：US5633605A

公开(公告)日：1997-05-27

申请号：US450764

申请日：1995-05-24

申请人： Jeffrey S. Zimmerman ,  John A. Fifield ,  Christopher P. Miller ,  Robert E. Busch

发明人： Jeffrey S. Zimmerman ,  John A. Fifield ,  Christopher P. Miller ,  Robert E. Busch

IPC分类号： G06F3/00 ,  G06F13/40 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/096

CPC分类号： G06F13/4077

摘要： A dynamic bus system with a central precharge device is disclosed that utilizes a controller circuit with a one-shot generator and write synchronizing circuits in combination with logic output modules having pull-up/down devices. The issuance of the output enable (OE) signals is interlocked with the turn-off of the precharge. Thus, data is written to the dynamic bus only when the precharge device is inactive, avoiding bus collisions. The resulting circuitry not only ensures the precharging of the bus before the data write to the bus, but will allow the synchronized OE signals to be issued during the same clock phase as the precharge signal.

摘要翻译： 公开了一种具有中央预充电装置的动态总线系统，其利用具有单触发发生器的控制器电路和与具有上拉/下拉器件的逻辑输出模块相结合的写入同步电路。 输出使能（OE）信号的发出与预充电的关断互锁。 因此，仅当预充电设备处于非活动状态时才将数据写入动态总线，避免总线冲突。 所产生的电路不仅可以确保在对总线的数据写入之前总线的预充电，而且允许在与预充电信号相同的时钟相位期间发出同步的OE信号。