公开(公告)号：US20090094567A1

公开(公告)日：2009-04-09

申请号：US11869176

申请日：2007-10-09

申请人： Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

发明人： Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/60 ,  H01L2223/6677 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such possibilities are based on the connection order, the size of the antennas, and the likelihood that charges will flow from the antennas through insulators of the devices. If a significant possibility for damage exists, the method can reduce the size of the antenna.

摘要翻译： 本文的方法实施例确定连接顺序，其中将连接有源器件连接到给定电路设计内的天线。 该方法还评估了这些与天线的连接在连接到天线的设备中将导致充电损坏的可能性。 这种可能性基于连接顺序，天线的尺寸以及电荷将从天线通过设备的绝缘体流过的可能性。 如果存在损坏的重大可能性，则该方法可以减小天线的尺寸。

公开(公告)号：US20070271540A1

公开(公告)日：2007-11-22

申请号：US11383565

申请日：2006-05-16

申请人： Chung-Ping Eng ,  Henry A. Bonges ,  Jeffrey S. Zimmerman ,  Terence B. Hook

发明人： Chung-Ping Eng ,  Henry A. Bonges ,  Jeffrey S. Zimmerman ,  Terence B. Hook

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  H01L27/0251

摘要： Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source of the second FET device are connected to a higher level connector and wherein the higher level connector eliminates a damaging current path between the first element and the second element.

摘要翻译： 公开了一种用于集成电路器件的保护电路，其中所述保护电路包括：连接到第一FET器件的栅极的第一元件; 以及连接到第二FET器件的栅极的第二元件，其中所述第一FET器件的漏极/源极和所述第二FET器件的漏极/源极连接到较高级别的连接器，并且其中所述较高级连接器消除了损坏 第一元件和第二元件之间的电流路径。

公开(公告)号：US07572650B2

公开(公告)日：2009-08-11

申请号：US11550853

申请日：2006-10-19

申请人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

发明人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC分类号： H01L21/00

CPC分类号： H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

摘要翻译： 用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US07712057B2

公开(公告)日：2010-05-04

申请号：US11955653

申请日：2007-12-13

申请人： Henry A. Bonges ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

发明人： Henry A. Bonges ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

摘要翻译： 公开了一种确定绝缘体上半导体（SOI）技术的允许天线极限的方法。 在一个实施例中，该方法可以包括：确定门上的天线面积; 确定源/漏极上的天线面积; 确定栅极和源极/漏极网之间的总栅极绝缘体面积; 并且计算作为网之间的总门绝缘体面积的函数的可允许天线面积，使得允许较大的总天线面积用于网之间较大的总栅极绝缘体面积。

公开(公告)号：US07173338B2

公开(公告)日：2007-02-06

申请号：US10708486

申请日：2004-03-06

申请人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

发明人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC分类号： H01L23/48

CPC分类号： H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

摘要翻译： 用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US07649262B2

公开(公告)日：2010-01-19

申请号：US12537328

申请日：2009-08-07

申请人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

发明人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC分类号： H01L23/48

CPC分类号： H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

摘要翻译： 用于抑制半导体处理中的局部金属沉淀形成（LMPF）的结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US20090294968A1

公开(公告)日：2009-12-03

申请号：US12537328

申请日：2009-08-07

申请人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

发明人： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC分类号： H01L23/532

CPC分类号： H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

摘要翻译： 用于抑制半导体处理中的局部金属沉淀形成（LMPF）的结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US20090158230A1

公开(公告)日：2009-06-18

申请号：US11955653

申请日：2007-12-13

申请人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

发明人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

摘要翻译： 公开了一种确定绝缘体上半导体（SOI）技术的允许天线极限的方法。 在一个实施例中，该方法可以包括：确定门上的天线面积; 确定源/漏极上的天线面积; 确定栅极和源极/漏极网之间的总栅极绝缘体面积; 并且计算作为网之间的总门绝缘体面积的函数的可允许天线面积，使得允许较大的总天线面积用于网之间较大的总栅极绝缘体面积。

公开(公告)号：US08619979B2

公开(公告)日：2013-12-31

申请号：US12823278

申请日：2010-06-25

申请人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

发明人： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

IPC分类号： G06F21/73 ,  H04L9/08

CPC分类号： G06F21/73 ,  H04L9/08 ,  H04L9/0866 ,  H04L9/3278

摘要： Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

摘要翻译： 公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。 在特定实施例中，电子设备可操作以产生对挑战的响应。 电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。 电子设备包括被配置为接收挑战的挑战输入。 挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。 该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。 该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

公开(公告)号：US20130256748A1

公开(公告)日：2013-10-03

申请号：US13431414

申请日：2012-03-27

申请人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

发明人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

IPC分类号： H01L29/73 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

摘要翻译： 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。