公开(公告)号：US07034897B2

公开(公告)日：2006-04-25

申请号：US10114679

申请日：2002-04-01

Applicant: Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

公开(公告)号：US06963613B2

公开(公告)日：2005-11-08

申请号：US10114797

申请日：2002-04-01

Applicant: Alexander G. MacInnis ,  Vivian Hsiun ,  Sheng Zhong ,  Xiaodong Xie ,  Kimming So ,  Jose′ R. Alvarez

Inventor： Alexander G. MacInnis ,  Vivian Hsiun ,  Sheng Zhong ,  Xiaodong Xie ,  Kimming So ,  Jose′ R. Alvarez

IPC: G06F9/38 ,  G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N7/12

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.

Abstract translation: 在解码系统中的模块之间进行通信的手段。 可变长度解码加速器经由协处理器接口与核心解码器处理器进行通信。 在一个实施例中，除了可变长度解码器之外，其他解码加速器适于向协处理器状态寄存器提供表示其状态的状态数据。 在另一个实施例中，解码加速器通过经由发布的写入操作向加速器提供命令并轮询加速器来控制，以确定该命令是否已被执行。 在另一个实施例中，第一硬件加速器经由协处理器接口与核心解码器处理器进行通信，并且除了第一硬件加速器之外，其他解码加速器适于将表示其状态的状态数据提供给协处理器状态 寄存器。

公开(公告)号：US08149909B1

公开(公告)日：2012-04-03

申请号：US11249213

申请日：2005-10-13

Applicant: Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

Inventor： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

IPC: H04N7/12 ,  H04N11/04

CPC classification number: H04N19/00096 ,  H04N19/126 ,  H04N19/14 ,  H04N19/176

Abstract: In some embodiments, macroblock-level encoding parameters are assigned to weighted Linear combinations of corresponding content-category-level encoding parameters. A macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics. Content-category-level statistics may be used in encoding subsequent frames.

Abstract translation: 在一些实施例中，宏块级编码参数被分配给相应内容类别级编码参数的加权线性组合。 宏块量化参数（QP）调制被设置为内容类别QP调制的加权线性组合。 内容类别可能会识别可能重叠的内容类型。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合块级统计信息生成内容类别级统计信息。 内容类别级统计可用于对后续帧进行编码。

公开(公告)号：US08126283B1

公开(公告)日：2012-02-28

申请号：US11250102

申请日：2005-10-13

Applicant: Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

Inventor： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

IPC: G06K9/46

CPC classification number: G06F17/30831 ,  G06F17/3079 ,  H04N19/124 ,  H04N19/136 ,  H04N19/142 ,  H04N19/147 ,  H04N19/149 ,  H04N19/176 ,  H04N19/196 ,  H04N19/85

Abstract: In some embodiments, content-category-level encoding statistical indicators (statistics) are assigned to weighted linear combinations of corresponding macroblock-level statistics. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A given macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Macroblock-level encoding parameters are generated by combining content-category-level parameters.

Abstract translation: 在一些实施例中，内容类别级编码统计指标（统计）被分配给相应宏块级统计的加权线性组合。 内容类别可能会识别潜在重叠的内容类型，如天空，水，草，皮肤和红色内容。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 给定宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合内容类别级参数来生成宏块级编码参数。

公开(公告)号：US08005147B2

公开(公告)日：2011-08-23

申请号：US11400949

申请日：2006-04-05

Applicant: Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Jose′ R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

Abstract translation: 一种用于解码数字视频数据流的系统和方法。 在一个方面，多个硬件加速模块与核心处理器一起使用。 加速器在解码管线中操作，其中在任何给定阶段，每个加速器对视频数据的特定宏块进行操作。 在随后的流水线阶段，每个加速器对数据流中的下一个宏块进行工作，该前一阶段的另一个加速器工作。 核心处理器在每个阶段轮询所有加速器。 当所有加速器在给定阶​​段完成任务时，核心处理器启动下一阶段。 在另一方面，采用两个可变长度解码器来同时解码视频帧的两个宏块行。 每个可变长度解码器用于对分配的行进行解码，并行并行地进行可变长度解码。 可变长度解码器作为流水线的一部分进行操作，其中可变长度解码器逐级交替解码宏块。

公开(公告)号：US20110090364A1

公开(公告)日：2011-04-21

申请号：US12979550

申请日：2010-12-28

Applicant: Jose R. Alvarez ,  Guy Cote

Inventor： Jose R. Alvarez ,  Guy Cote

IPC: H04N5/225

CPC classification number: H04N19/59 ,  H04N19/117 ,  H04N19/124 ,  H04N19/132 ,  H04N19/14 ,  H04N19/146 ,  H04N19/17 ,  H04N19/176 ,  H04N19/61 ,  H04N19/85

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit.

Abstract translation: 一种包括第一电路和第二电路的装置。 第一电路可以被配置为使用编码相关信息来执行图像信号处理。 第二电路可以被配置为使用图像信号处理相关信息对图像数据进行编码，其中所述第一电路还被配置为将所述图像信号处理相关信息传递到所述第二电路，并且所述第二电路还被配置为将所述编码相关信息传递到 说第一个电路。

公开(公告)号：US07007031B2

公开(公告)日：2006-02-28

申请号：US10114886

申请日：2002-04-01

Applicant: Alexander G. MacInnis ,  Jose′ R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose′ R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: G06F7/00 ,  G06F17/00 ,  G06F12/00 ,  G06F12/14 ,  G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  Y10S707/99942

Abstract: System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.