公开(公告)号：US20110202236A1

公开(公告)日：2011-08-18

申请号：US13022346

申请日：2011-02-07

申请人： Mario Galasso ,  Joseph Franklin ,  Andrew Laird ,  Robert C. Fox

发明人： Mario Galasso ,  Joseph Franklin ,  Andrew Laird ,  Robert C. Fox

IPC分类号： B60G17/015 ,  B60Q1/00

CPC分类号： F16F9/3264 ,  B62K25/04 ,  B62K25/286 ,  F16F2228/08

摘要： Methods and apparatus of a system for vehicles comprising a vehicle suspension, a sensor operable to measure an operational characteristic of the vehicle suspension, and a processor in communication with the sensor that is operable to suggest an operational setting of the vehicle suspension in response to an input from the sensor corresponding to the operational characteristic. A method for adjusting a suspension of a vehicle may comprise receiving suspension data with a processor, calculating a suspension setting suggestion with the processor, communicating the suspension setting suggestion to a user interface device, and adjusting the suspension based on the suspension setting suggestion.

摘要翻译： 一种用于车辆的系统的方法和装置，包括车辆悬架，可操作以测量车辆悬架的操作特性的传感器，以及与所述传感器通信的处理器，所述处理器可操作以响应于所述车辆悬架建议所述车辆悬架的操作设置 来自传感器的输入对应于操作特性。 一种用于调整车辆悬架的方法可以包括用处理器接收悬架数据，用处理器计算悬架设置建议，将暂停设置建议传达到用户界面设备，以及基于暂停设置建议来调整暂停。

公开(公告)号：US20090322054A1

公开(公告)日：2009-12-31

申请号：US12493412

申请日：2009-06-29

申请人： William M. Becker ,  Sante M. Pelot ,  Joseph Franklin

发明人： William M. Becker ,  Sante M. Pelot ,  Joseph Franklin

IPC分类号： B62K21/02 ,  F16F9/34 ,  F16F9/49 ,  G05D7/00

CPC分类号： F16F9/468 ,  B62K25/08 ,  Y10T137/0357

摘要： A method and apparatus for reducing cavitation and its effects in a damper. The damper includes a flow dividing structure. In one embodiment, the structure is disposed in a valve including an annular flow path constructed and arranged to separate fluid into substantially separate streams as the fluid passes through the annular path.

摘要翻译： 一种用于减少气蚀及其在阻尼器中的作用的方法和装置。 阻尼器包括分流结构。 在一个实施例中，该结构设置在包括环形流动路径的阀中，所述环形流动路径构造和布置成当流体通过环形路径时将流体分离成基本上分离的流。

公开(公告)号：US07627701B2

公开(公告)日：2009-12-01

申请号：US12120419

申请日：2008-05-14

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F5/00 ,  G06F15/16

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US07506081B2

公开(公告)日：2009-03-17

申请号：US10850219

申请日：2004-05-20

申请人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： G06F3/00

CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093

摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.

摘要翻译： 网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。 存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。 通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。 类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。 因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。

公开(公告)号：US20070255020A1

公开(公告)日：2007-11-01

申请号：US11708244

申请日：2007-02-20

申请人： Daniel Lee Martin ,  Joseph Franklin Knight ,  Benjamin Fredrick Barton ,  Damon Bryan Shackelford

发明人： Daniel Lee Martin ,  Joseph Franklin Knight ,  Benjamin Fredrick Barton ,  Damon Bryan Shackelford

IPC分类号： C08G63/16 ,  C08G63/02 ,  C08G85/00

CPC分类号： C08G63/199 ,  C08G63/78

摘要： Disclosed is a process for the preparation of high molecular weight polyesters by reacting one or more dicarboxylic acids directly with 1,4-cyclohexanedimethanol and, optionally, one or more diols. The process uses an overall diol to dicarboxylic acid molar ratio of about 0.97 to about 1.2 and an incremental addition of either the diacid or diol components. The process provides a shorter total reaction time and, thus, lessens the thermal degradation of polyester which may result in high color and reduced molecular weight.

摘要翻译： 公开了通过使一种或多种二羧酸直接与1,4-环己烷二甲醇和任选的一种或多种二醇反应来制备高分子量聚酯的方法。 该方法使用总体二醇与二羧酸的摩尔比为约0.97至约1.2，并且增加二酸或二醇组分的添加量。 该方法提供较短的总反应时间，从而降低聚酯的热降解，这可能导致高的颜色和降低的分子量。

公开(公告)号：US07130916B2

公开(公告)日：2006-10-31

申请号：US09791336

申请日：2001-02-23

申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F15/167 ,  G06F12/00 ,  G06F12/16 ,  G06F13/28 ,  G06F9/44 ,  H04L12/54 ,  G06F15/16 ,  G06F12/14 ,  G06F13/00 ,  G06F3/00 ,  G06F9/46

CPC分类号： H04L49/3081 ,  G06F13/4243 ,  H04L2012/5681

摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

公开(公告)号：US06910092B2

公开(公告)日：2005-06-21

申请号：US10016800

申请日：2001-12-10

申请人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

发明人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/42

CPC分类号： G06F13/4265

摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

摘要翻译： 网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。 可选的调度器芯片耦合到数据流芯片。 命名的组件被复制以创建对称的入口和出口结构。 芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。

公开(公告)号：US06836480B2

公开(公告)日：2004-12-28

申请号：US09839079

申请日：2001-04-20

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： H04L1256

CPC分类号： H04L49/901 ,  H04L12/1881 ,  H04L47/10 ,  H04L47/20 ,  H04L49/90

摘要： Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.

摘要翻译： 数据结构，方法和相关的传输系统，用于网络处理器上的组播传输，以便最大限度地减少组播传输内存的需求并解决端口性能差异。 将网络处理器上的组播传输的帧数据读入与各种控制结构和参考帧相关联的缓冲器。 参考帧和相关联的控制结构允许在不创建帧的多个拷贝的情况下对多播目标进行服务。 此外，相同的参考帧和控制结构允许为每个多播目标分配的缓冲区返回到空闲缓冲器队列，而不等待所有多播传输完成。

公开(公告)号：US06721885B1

公开(公告)日：2004-04-13

申请号：US09658130

申请日：2000-09-08

申请人： Joseph Wayne Freeman ,  Joseph Franklin Garvey ,  Steven D. Goodman ,  William Fred Keown, Jr. ,  Randall S. Springfield

发明人： Joseph Wayne Freeman ,  Joseph Franklin Garvey ,  Steven D. Goodman ,  William Fred Keown, Jr. ,  Randall S. Springfield

IPC分类号： G06F15177

CPC分类号： G06F9/4401 ,  G06F11/2289

摘要： Disclosed is a method for reducing power-up time and avoiding customer-induced failures of computer systems during power-up. An intrusion switch, which is connected to the inside frame of the computer system is utilized. The intrusion switch signals the BIOS of the computer system whenever the cover of the computer's system unit is opened. The BIOS controls the POST operation during power-up of the computer system. During an initial power-up of the computer system, the POST configuration code examines and configures the hardware and sets the applicable registers, etc. At the end of the POST configuration code, the register values are stored in non-volatile storage. During a subsequent power-up of the computer system, a check is made to see if the cover of the system had been opened. When the cover has not been opened, the BIOS assumes that no changed has occurred in the hardware configuration and the BIOS restores the register values from non-volatile storage without completing the POST operation. When the cover has been opened, the BIOS discards the register values and initiates the POST operation, i.e., a full configuration operation is performed and new values stored in the registers and non-volatile storage element.

摘要翻译： 公开了一种在上电期间减少上电时间并避免客户导致的计算机系统故障的方法。 使用连接到计算机系统的内部框架的入侵开关。 每当打开计算机系统单元的盖子时，入侵开关就会通知计算机系统的BIOS。 BIOS在电脑系统启动期间控制POST操作。 在计算机系统的初始上电期间，POST配置代码检查和配置硬件并设置适用的寄存器等。在POST配置代码结束时，寄存器值存储在非易失性存储器中。 在计算机系统的随后上电期间，检查系统的盖是否已打开。 当盖子尚未打开时，BIOS假定在硬件配置中没有发生任何变化，BIOS会从非易失性存储器中恢复寄存器值，而无需完成POST操作。 当盖子打开时，BIOS将丢弃寄存器值并启动POST操作，即执行完整配置操作，并将新值存储在寄存器和非易失性存储元件中。

公开(公告)号：US5737524A

公开(公告)日：1998-04-07

申请号：US446390

申请日：1995-05-22

申请人： Ariel Cohen ,  William Gavin Holland ,  Joseph Franklin Logan ,  Avi Parash

发明人： Ariel Cohen ,  William Gavin Holland ,  Joseph Franklin Logan ,  Avi Parash

IPC分类号： G06F13/36 ,  G06F13/14 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F15/177

摘要： An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.

摘要翻译： 用于在外围组件互连（PCI）计算机中使用的适配器或附加卡包括将卡耦合到PCI总线的通用模块。 该模块包括一组选择性可编程配置寄存器，它们由适配器上的微处理器加载。 模块上的电路布置发出一个命令，禁止PCI处理器访问配置寄存器，直到完全加载。