公开(公告)号：US07263117B2

公开(公告)日：2007-08-28

申请号：US10409141

申请日：2003-04-09

Applicant: Ki-Jun Lee ,  Gurpreet Bhullar

Inventor： Ki-Jun Lee ,  Gurpreet Bhullar

IPC: H03H11/26

CPC classification number: H03K5/133 ,  H03K5/13 ,  H03K5/131 ,  H03K2005/00032

Abstract: A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract translation: 描述了包括各自具有选择性调整的粗略和微小延迟部分的模拟延迟元件的延迟线。 粗延迟部分接收输入时钟信号并产生具有基于预定粗延迟设置的斜率的斜坡信号。 精细延迟部分基于预定的精细延迟设置产生阈值电压。 比较器比较粗略延迟斜坡信号电压和精细延迟阈值电压，并且当斜坡信号电压超过精细延迟阈值电压时产生输出时钟信号。 基于32位二进制输入信号，粗略延迟是线性可调的，精细延迟是基于5位二进制输入信号进行二进制加权调整的。 粗延迟部分和精细延迟部分由延迟线控制电路控制，延迟线控制电路将输出时钟信号的反馈版本与输入时钟信号进行比较，并提供控制信号以在延迟线中增加或减少粗略和精细的延迟。

公开(公告)号：US06559699B2

公开(公告)日：2003-05-06

申请号：US09985972

申请日：2001-11-07

Applicant: Ki-Jun Lee ,  Gurpreet Bhullar

Inventor： Ki-Jun Lee ,  Gurpreet Bhullar

IPC: H03H1126

CPC classification number: H03K5/133 ,  H03K5/13 ,  H03K5/131 ,  H03K2005/00032

Abstract: A delay line comprised of analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

公开(公告)号：US5781485A

公开(公告)日：1998-07-14

申请号：US563404

申请日：1995-11-30

Applicant: Ki-Jun Lee ,  Jin-Ki Kim

Inventor： Ki-Jun Lee ,  Jin-Ki Kim

IPC: G01R31/28 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/46 ,  G11C29/56 ,  G11C13/00

CPC classification number: G11C29/46

Abstract: An apparatus and method for controlling an operating mode in a semiconductor memory device is provided. During test mode, test mode selection signals are supplied to the memory device according to test mode commands received from an external pad and decoded internally. During both test mode and user mode, user mode selection signals are supplied to the memory device according to user mode commands received from an external pad and decoded internally. Upon receipt of a test release command, test mode commands are fusably disabled, such that entry into test mode and decoding of test mode commands is thereafter prevented.

Abstract translation: 提供一种用于控制半导体存储器件中的工作模式的装置和方法。 在测试模式期间，根据从外部焊盘接收的测试模式命令将测试模式选择信号提供给存储器件，并在内部进行解码。 在测试模式和用户模式期间，根据从外部焊盘接收的用户模式命令将用户模式选择信号提供给存储器件，并在内部进行解码。 在接收到测试释放命令时，测试模式命令被可靠地禁用，从而防止进入测试模式和解码测试模式命令。