公开(公告)号：US20100177590A1

公开(公告)日：2010-07-15

申请号：US12455727

申请日：2009-06-04

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/18 ,  H03L7/00

CPC classification number: G11C8/18 ,  G11C7/1027 ,  G11C7/1066

Abstract: A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.

Abstract translation: 突发模式控制单元包括：脉冲串周期信号产生单元，用于产生在脉冲串模式运行周期期间使能的脉冲串周期信号;脉冲串脉冲发生单元，用于产生脉冲脉冲脉冲，脉冲串脉冲产生单元在 响应于读命令和写命令，脉冲串周期信号的使能周期，以及用于接收脉冲串信号和时钟信号的列存取信号产生单元，并产生一列控制数据输入和输出的列存取信号 突发模式运行期间。

公开(公告)号：US20100157717A1

公开(公告)日：2010-06-24

申请号：US12493755

申请日：2009-06-29

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/00 ,  G11C8/18 ,  G11C7/00

CPC classification number: G11C7/222 ,  G11C7/1027 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract translation: 半导体集成电路包括命令解码器，移位寄存器单元和命令地址锁存单元。 命令解码器响应于定义写入和读取模式的外部命令，并且被配置为使用上升或下降时钟根据外部命令提供写入命令或读取命令。 移位寄存器单元被配置为响应写入命令将外部地址和写入命令移位写入延迟。 列地址锁存单元被配置为在读取模式下锁存并提供外部地址作为列地址，并锁存从移位寄存器单元提供的写入地址，并将写入地址作为列地址提供给 写模式。

公开(公告)号：US20090231947A1

公开(公告)日：2009-09-17

申请号：US12337521

申请日：2008-12-17

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/06 ,  G11C29/00

CPC classification number: G11C8/06 ,  G11C29/18

Abstract: A semiconductor IC in which a least significant bit of an external address signal is fixed to a signal level, the semiconductor integrated circuit includes an address control circuit configured to produce a carry signal, when a test mode signal is activated, in response to a column command signal and output an address signal, which is sequentially increased from an initial internal address signal, by latching the external address signal as the initial internal address signal and combining the latched initial internal address signal and the carry signal.

Abstract translation: 一种半导体IC，其中外部地址信号的最低有效位被固定为信号电平，所述半导体集成电路包括地址控制电路，其被配置为当测试模式信号被激活时响应于列而产生进位信号 通过锁存外部地址信号作为初始内部地址信号并组合锁存的初始内部地址信号和进位信号，输出从初始内部地址信号顺序增加的地址信号。

公开(公告)号：US20090180336A1

公开(公告)日：2009-07-16

申请号：US12319877

申请日：2009-01-13

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C2211/4065

Abstract: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a period measurement start signal generator configured to receive a self-refresh signal and an oscillation signal, to allow a self-refresh operation to be performed, and generate a period measurement start signal, to set the time that the oscillation signal is enabled, and a refresh period output unit configured to receive the period measurement start signal and the oscillation signal, and generate a refresh period output signal that is enabled for a period from the time that the period measurement start signal is enabled to a time that the oscillation signal is enabled.

Abstract translation: 公开了一种半导体器件的自刷新周期测量电路，其中包括周期测量开始信号发生器，其被配置为接收自刷新信号和振荡信号，以允许执行自刷新操作，并且生成 周期测量开始信号，以设定振荡信号被使能的时间;以及刷新周期输出单元，被配置为接收周期测量开始信号和振荡信号，并产生一个刷新周期输出信号，该刷新周期输出信号从 时间测量开始信号使能到振荡信号使能的时间。

公开(公告)号：US07301841B2

公开(公告)日：2007-11-27

申请号：US11320650

申请日：2005-12-30

Applicant: Kyong-Ha Lee

Inventor： Kyong-Ha Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50016 ,  G11C2211/4061

Abstract: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode; and a self-refresh block for performing the self-refresh operation in response to an output of the first period selector.

Abstract translation: 本发明提供适用于测试对热温度应力弱的细胞的自刷新周期。 一种用于控制半导体存储器件中的自刷新操作的装置包括：第一周期选择器，用于产生具有恒定周期的周期固定脉冲信号和基于温度的可变周期的周期可变脉冲信号 半导体存储器件处于测试模式; 以及自刷新块，用于响应于第一周期选择器的输出执行自刷新操作。

公开(公告)号：US08254202B2

公开(公告)日：2012-08-28

申请号：US12826906

申请日：2010-06-30

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/00

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C11/4076

Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.

Abstract translation: 内部命令生成电路包括脉冲串脉冲发生单元和脉冲移位单元。 突发脉冲发生单元被配置为接收用于读取或写入操作的命令，并且生成第一突发脉冲。 脉冲移位单元被配置为移位第一突发脉冲并产生内部命令。

公开(公告)号：US08068383B2

公开(公告)日：2011-11-29

申请号：US12337521

申请日：2008-12-17

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/00

CPC classification number: G11C8/06 ,  G11C29/18

Abstract: A semiconductor IC in which a least significant bit of an external address signal is fixed to a signal level, the semiconductor integrated circuit includes an address control circuit configured to produce a carry signal, when a test mode signal is activated, in response to a column command signal and output an address signal, which is sequentially increased from an initial internal address signal, by latching the external address signal as the initial internal address signal and combining the latched initial internal address signal and the carry signal.

Abstract translation: 一种半导体IC，其中外部地址信号的最低有效位被固定为信号电平，所述半导体集成电路包括地址控制电路，其被配置为当测试模式信号被激活时响应于列而产生进位信号 通过锁存外部地址信号作为初始内部地址信号并组合锁存的初始内部地址信号和进位信号，输出从初始内部地址信号顺序增加的地址信号。

公开(公告)号：US08027222B2

公开(公告)日：2011-09-27

申请号：US12455727

申请日：2009-06-04

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C7/1027 ,  G11C7/1066

Abstract: A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.

Abstract translation: 突发模式控制单元包括：脉冲串周期信号产生单元，用于产生在脉冲串模式运行周期期间使能的脉冲串周期信号;脉冲串脉冲发生单元，用于产生脉冲脉冲脉冲，脉冲串脉冲产生单元在 响应于读命令和写命令，脉冲串周期信号的使能周期，以及用于接收脉冲串信号和时钟信号的列存取信号产生单元，并产生一列控制数据输入和输出的列存取信号 突发模式运行期间。

公开(公告)号：US08023357B2

公开(公告)日：2011-09-20

申请号：US12459362

申请日：2009-06-30

Applicant: Kyong Ha Lee

Inventor： Kyong Ha Lee

IPC: G11C8/00

CPC classification number: G11C8/12

Abstract: A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group, a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group, and a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group.

Abstract translation: 半导体存储器包括地址转换电路，其锁存地址和存储体信号，并产生用于激活第二组组的数据存取路径的锁存地址，并根据存储体信号的电平转换锁存器地址，并产生变量 用于激活第一组组的数据访问路径的地址;解码可变地址并产生用于激活第一组组的数据访问路径的第一输出使能信号的第一列解码器，以及解码锁存器的第二列解码器 地址并产生用于激活第二组组的数据访问路径的第二输出使能信号。

公开(公告)号：US20110128811A1

公开(公告)日：2011-06-02

申请号：US12826906

申请日：2010-06-30

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/18

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C11/4076

Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.

Abstract translation: 内部命令生成电路包括脉冲串脉冲发生单元和脉冲移位单元。 突发脉冲发生单元被配置为接收用于读取或写入操作的命令，并且生成第一突发脉冲。 脉冲移位单元被配置为移位第一突发脉冲并产生内部命令。