公开(公告)号：US20140344552A1

公开(公告)日：2014-11-20

申请号：US13895595

申请日：2013-05-16

Applicant: Frank Binns ,  Matthew C. Merten ,  Mayank Bomb ,  Beeman C. Strong ,  Peter Lachner ,  Jason W. Brandt ,  Itamar Kazachinsky ,  Ofer Levy ,  MD A. Rahman

Inventor： Frank Binns ,  Matthew C. Merten ,  Mayank Bomb ,  Beeman C. Strong ,  Peter Lachner ,  Jason W. Brandt ,  Itamar Kazachinsky ,  Ofer Levy ,  MD A. Rahman

IPC: G06F9/30

CPC classification number: G06F11/3636 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3476 ,  G06F11/348 ,  G06F2201/865

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

Abstract translation: 根据本文公开的实施例，提供了用于在指令跟踪系统中提供具有周期性同步点的处理设备的状态的系统和方法。 例如，该方法可以包括基于分组日志中的唯一字节模式生成边界分组。 边界包提供了分组解码的起始点。 该方法还可以包括基于处理器的状态信息生成多个状态分组。 当输出到分组日志中时，多个状态分组遵循边界分组。

公开(公告)号：US20140310504A1

公开(公告)日：2014-10-16

申请号：US13861009

申请日：2013-04-11

Applicant: VIJAYKUMAR B. KADGI ,  JEREMY R. ANDERSON ,  JAMES D. HADLEY ,  TONG LI ,  MATTHEW C. MERTEN

Inventor： VIJAYKUMAR B. KADGI ,  JEREMY R. ANDERSON ,  JAMES D. HADLEY ,  TONG LI ,  MATTHEW C. MERTEN

IPC: G06F9/30

CPC classification number: G06F9/30105 ,  G06F8/443 ,  G06F9/30032 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

Abstract translation: 涉及移动消除的数据处理操作中标志跟踪的系统和方法。 示例性处理系统包括包括多个物理寄存器值的第一数据结构; 第二数据结构，包括引用第一数据结构的元素的多个指针; 包括多个移动消除集合的第三数据结构，每个移动消除集合包括表示两个或多个逻辑数据寄存器的两个或多个位，所述第三数据结构还包括与每个移动消除集相关联的至少一个位，所述至少一个 位表示一个或多个逻辑标志寄存器; 第四数据结构，包括与标志寄存器共享第一数据结构的元素的数据寄存器的标识符; 以及配置为执行移动消除操作的移动消除逻辑。

公开(公告)号：US20130311758A1

公开(公告)日：2013-11-21

申请号：US13993792

申请日：2012-03-30

Applicant: Paul Caprioli ,  Matthew C. Merten ,  Muawya M. Al-Otoom ,  Omar M. Shaikh ,  Abhay S. Kanhere ,  Suresh Srinivas ,  Koichi Yamada ,  Vivek Thakkar ,  Pawel Osciak

Inventor： Paul Caprioli ,  Matthew C. Merten ,  Muawya M. Al-Otoom ,  Omar M. Shaikh ,  Abhay S. Kanhere ,  Suresh Srinivas ,  Koichi Yamada ,  Vivek Thakkar ,  Pawel Osciak

IPC: G06F9/38

CPC classification number: G06F11/3466 ,  G06F8/40 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/3842 ,  G06F9/4552 ,  G06F11/073 ,  G06F11/3616 ,  G06F11/3652

Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

Abstract translation: 通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。 运行期间的硬件标识内存中包含潜在优化指令的代码页。 硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。 当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。 代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。 然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。

公开(公告)号：US11080045B2

公开(公告)日：2021-08-03

申请号：US13993483

申请日：2011-12-22

Applicant: Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US10235180B2

公开(公告)日：2019-03-19

申请号：US13723684

申请日：2012-12-21

Applicant: Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

Inventor： Srikanth T. Srinivasan ,  Matthew C. Merten ,  Bambang Sutanto ,  Rahul R. Kulkarni ,  Justin M. Deinlein ,  James D. Hadley

IPC: G06F9/30 ,  G06F9/38

Abstract: A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

公开(公告)号：US09542191B2

公开(公告)日：2017-01-10

申请号：US13993792

申请日：2012-03-30

Applicant: Paul Caprioli ,  Matthew C. Merten ,  Muawya M. Al-Otoom ,  Omar M. Shaikh ,  Abhay S. Kanhere ,  Suresh Srinivas ,  Koichi Yamada ,  Vivek Thakkar ,  Pawel Osciak

Inventor： Paul Caprioli ,  Matthew C. Merten ,  Muawya M. Al-Otoom ,  Omar M. Shaikh ,  Abhay S. Kanhere ,  Suresh Srinivas ,  Koichi Yamada ,  Vivek Thakkar ,  Pawel Osciak

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/45 ,  G06F9/455

CPC classification number: G06F11/3466 ,  G06F8/40 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/3842 ,  G06F9/4552 ,  G06F11/073 ,  G06F11/3616 ,  G06F11/3652

Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

Abstract translation: 通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。 运行期间的硬件标识内存中包含潜在优化指令的代码页。 硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。 当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。 代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。 然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。

公开(公告)号：US09354875B2

公开(公告)日：2016-05-31

申请号：US13728273

申请日：2012-12-27

Applicant: Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

Inventor： Matthew C. Merten ,  Justin M. Deinlein ,  Yury N. Ilin ,  Alexandre J. Farcy ,  Tong Li ,  Srikanth T. Srinivasan

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3885

Abstract: An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

Abstract translation: 在处理器中提供增强的循环流检测机制以降低功耗。 处理器包括解码器，用于将循环中的指令解码为微操作，以及循环流检测器，用于检测微操作中环路的存在。 处理器还包括循环特性跟踪器单元，用于识别解码器下游的不被循环中的微操作使用的硬件组件，以及禁用所识别的硬件组件。 该处理器还包括执行电路，以在所识别的硬件组件被禁用的情况下执行循环中的微操作。

公开(公告)号：US20150095627A1

公开(公告)日：2015-04-02

申请号：US14040016

申请日：2013-09-27

Applicant: Mark J. DECHENE ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Tong LI ,  Christine E. WANG

Inventor： Mark J. DECHENE ,  Srikanth T. SRINIVASAN ,  Matthew C. MERTEN ,  Tong LI ,  Christine E. WANG

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F8/445 ,  G06F8/47 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/45508 ,  G06F9/461

Abstract: In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.

Abstract translation: 响应于检测到一个或多个条件被满足，可以创建线程的当前状态的检查点。 可以将一个或多个不完整的指令从重新排序缓冲器的第一级移动到重新排序缓冲器的第二级。 每个不完整的指令可能正在执行或等待执行。

公开(公告)号：US20150032998A1

公开(公告)日：2015-01-29

申请号：US13997243

申请日：2012-02-02

Applicant: Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

Inventor： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3859

Abstract: An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.

Abstract translation: 这里描述了一种用于提供猜测控制指令的装置和方法。 提供xAcquire和xRelease指令来定义关键部分。 在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。 因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。 但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。 此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。 此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

公开(公告)号：US20150006868A1

公开(公告)日：2015-01-01

申请号：US13930501

申请日：2013-06-28

Applicant: Ilya Wagner ,  Matthew C. Merten ,  Frank Binns ,  Christine E. Wang ,  Mayank Bomb ,  Tong Li ,  Thilo Schmitt ,  MD A. Rahman

Inventor： Ilya Wagner ,  Matthew C. Merten ,  Frank Binns ,  Christine E. Wang ,  Mayank Bomb ,  Tong Li ,  Thilo Schmitt ,  MD A. Rahman

IPC: G06F9/38

CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F2201/81

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

Abstract translation: 根据本文公开的实施例，提供了用于最小化带宽以压缩指令跟踪系统的输出流的系统和方法。 例如，该方法可以包括将IT模块的跟踪中的当前指令识别为条件分支（CB）指令。 该方法包括执行以下步骤：生成包括具有CB指令的结果的指示的字节模式的CB分组，或者将CB指令的结果的指示添加到现有CB分组的字节模式。 该方法包括当跟踪中的后续指令不是CB指令时产生分组。 该分组与CB分组不同。 该方法还包括当分组可延迟时将分组添加到延迟队列中。 该方法还包括将后续的延迟分组的CB分组输出到分组日志中。