公开(公告)号：US09672019B2

公开(公告)日：2017-06-06

申请号：US12978557

申请日：2010-12-25

Applicant: David J. Sager ,  Ruchira Sasanka ,  Ron Gabor ,  Shlomo Raikin ,  Joseph Nuzman ,  Leeor Peled ,  Jason A. Domer ,  Ho-Seop Kim ,  Youfeng Wu ,  Koichi Yamada ,  Tin-Fook Ngai ,  Howard H. Chen ,  Jayaram Bobba ,  Jeffery J. Cook ,  Omar M. Shaikh ,  Suresh Srinivas

Inventor： David J. Sager ,  Ruchira Sasanka ,  Ron Gabor ,  Shlomo Raikin ,  Joseph Nuzman ,  Leeor Peled ,  Jason A. Domer ,  Ho-Seop Kim ,  Youfeng Wu ,  Koichi Yamada ,  Tin-Fook Ngai ,  Howard H. Chen ,  Jayaram Bobba ,  Jeffery J. Cook ,  Omar M. Shaikh ,  Suresh Srinivas

IPC: G06F9/45 ,  G06F9/38 ,  G06F9/54 ,  G06F11/36

CPC classification number: G06F8/4442 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/54 ,  G06F11/3612 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2213/0038

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

公开(公告)号：US20130311758A1

公开(公告)日：2013-11-21

申请号：US13993792

申请日：2012-03-30

Applicant: Paul Caprioli ,  Matthew C. Merten ,  Muawya M. Al-Otoom ,  Omar M. Shaikh ,  Abhay S. Kanhere ,  Suresh Srinivas ,  Koichi Yamada ,  Vivek Thakkar ,  Pawel Osciak

Inventor： Paul Caprioli ,  Matthew C. Merten ,  Muawya M. Al-Otoom ,  Omar M. Shaikh ,  Abhay S. Kanhere ,  Suresh Srinivas ,  Koichi Yamada ,  Vivek Thakkar ,  Pawel Osciak

IPC: G06F9/38

CPC classification number: G06F11/3466 ,  G06F8/40 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/3842 ,  G06F9/4552 ,  G06F11/073 ,  G06F11/3616 ,  G06F11/3652

Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

Abstract translation: 通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。 运行期间的硬件标识内存中包含潜在优化指令的代码页。 硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。 当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。 代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。 然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。

公开(公告)号：US20130198458A1

公开(公告)日：2013-08-01

申请号：US13785561

申请日：2013-03-05

Applicant: SEBASTIAN WINKEL ,  KOICHI YAMADA ,  SURESH SRINIVAS ,  JAMES E. SMITH

Inventor： SEBASTIAN WINKEL ,  KOICHI YAMADA ,  SURESH SRINIVAS ,  JAMES E. SMITH

IPC: G06F12/08

CPC classification number: G06F9/3017 ,  G06F9/455 ,  G06F12/0873 ,  G06F12/0875

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器可以在多种模式下操作，包括直接执行模式和仿真执行模式。 更具体地，处理器可以在部分仿真模型中操作，其中以直接执行模式直接处理源指令集架构（ISA）指令，并且在仿真执行模式中处理由仿真引擎生成的转换代码。 实施例还可以使用可以存储在处理器的一个或多个存储器和系统中的其他地方的信息来提供模式之间的有效转换。 描述和要求保护其他实施例。

公开(公告)号：US20050132336A1

公开(公告)日：2005-06-16

申请号：US10735855

申请日：2003-12-16

Applicant: Jacob Gotwals ,  Suresh Srinivas

Inventor： Jacob Gotwals ,  Suresh Srinivas

IPC: G06F9/44 ,  G06F11/30 ,  G06F15/00 ,  G21C17/00

CPC classification number: G06F11/3604

Abstract: Analyzing profile data of a software application in terms of high-level instances of the software application.

Abstract translation: 根据软件应用程序的高级实例分析软件应用程序的配置文件数据。

公开(公告)号：US09417855B2

公开(公告)日：2016-08-16

申请号：US13995400

申请日：2011-09-30

Applicant: Abhay S. Kanhere ,  Paul Caprioli ,  Koichi Yamada ,  Suriya Madras-Subramanian ,  Suresh Srinivas

Inventor： Abhay S. Kanhere ,  Paul Caprioli ,  Koichi Yamada ,  Suriya Madras-Subramanian ,  Suresh Srinivas

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F8/40 ,  G06F8/456 ,  G06F8/51 ,  G06F9/30109 ,  G06F9/30185 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/4552

Abstract: A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.

Abstract translation: 微架构可以提供硬件和软件协同设计的动态二进制翻译。 微架构可以调用执行动态二进制转换的方法。 该方法可以包括执行针对第一指令集编译的原始软件代码，使用处理器硬件来检测软件代码中的热点并将控制传递给二进制翻译翻译器，确定用于翻译的热点区域，使用 第二指令集，将转换的代码放置在转换高速缓存中，从翻译的高速缓存中执行转换的代码，并且在转换的代码完成执行之后转换回原始软件代码。

公开(公告)号：US20140025901A1

公开(公告)日：2014-01-23

申请号：US14033463

申请日：2013-09-21

Applicant: Quinn A. Jacobson ,  Anne C. Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham Chinya ,  Bratin Saha ,  Ali-Reza Adi-Tabatabai ,  Gad Sheaffer

Inventor： Quinn A. Jacobson ,  Anne C. Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham Chinya ,  Bratin Saha ,  Ali-Reza Adi-Tabatabai ,  Gad Sheaffer

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F11/3471 ,  G06F11/3648 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/145 ,  G06F2201/865

Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Abstract translation: 使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

公开(公告)号：US20110153992A1

公开(公告)日：2011-06-23

申请号：US12645668

申请日：2009-12-23

Applicant: Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

Inventor： Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

IPC: G06F9/44 ,  G06F9/46

CPC classification number: G06F9/528 ,  G06F8/458 ,  G06F9/3842 ,  G06F9/45516 ,  G06F9/526 ,  G06F17/30168 ,  G06F17/30362 ,  Y10S707/99938

Abstract: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.

Abstract translation: 公开了用于管理对象锁的示例性方法和装置。 所公开的示例性方法包括从处理器接收对象锁定请求，与对象锁定代码相关联的锁定请求以锁定对象，以及基于处理器的类型生成对象锁定旁路代码，执行对象锁定旁路代码 在受管运行时响应于接收到对象锁定请求。 示例性方法还包括识别与处理器相关联的指令集架构（ISA）的类型，基于所识别的ISA调用处理器的检查点指令，当对象不受约束时暂停对象锁定代码执行和执行目标代码， 并允许对象锁定代码在对象被竞争时执行。

公开(公告)号：US20070156967A1

公开(公告)日：2007-07-05

申请号：US11321133

申请日：2005-12-29

Applicant: Michael Bond ,  Shirish Aundhe ,  Greg Eastman ,  Suresh Srinivas

Inventor： Michael Bond ,  Shirish Aundhe ,  Greg Eastman ,  Suresh Srinivas

IPC: G06F12/00

CPC classification number: G06F12/0862 ,  G06F12/0253 ,  G06F2212/6024

Abstract: In one embodiment, an object oriented programming language can pre-fetch objects and fields within those objects to a cache memory. A hardware performance monitor can be used to identify loads that read from an address that is frequently absent from a memory. Instrumentation can be used to mark the objects that include the frequently missed address. A compiler can identify chains of objects that are frequently absent from memory. The chains of objects can be pre-fetched without regard to the types of object. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，面向对象的编程语言可以将这些对象内的对象和字段预取到高速缓冲存储器。 可以使用硬件性能监视器来识别从存储器中经常缺少的地址读取的加载。 仪器可用于标记包含经常错过的地址的对象。 编译器可以识别经常在内存中不存在的对象链。 可以预取对象的链，而不考虑对象的类型。 描述和要求保护其他实施例。

公开(公告)号：US09189233B2

公开(公告)日：2015-11-17

申请号：US13533821

申请日：2012-06-26

Applicant: Ruchira Sasanka ,  Abhinav Das ,  Jeffrey J. Cook ,  Jayaram Bobba ,  Arvind Krishnaswamy ,  David J. Sager ,  Suresh Srinivas

Inventor： Ruchira Sasanka ,  Abhinav Das ,  Jeffrey J. Cook ,  Jayaram Bobba ,  Arvind Krishnaswamy ,  David J. Sager ,  Suresh Srinivas

IPC: G06F9/00 ,  G06F9/30 ,  G06F11/36 ,  G06F9/38 ,  G06F9/54 ,  G06F9/45

CPC classification number: G06F11/3612 ,  G06F8/456 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/54 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2213/0038

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.

Abstract translation: 描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。 例如，根据一个实施例的方法包括：分析执行程序代码的单线程区域，所述分析包括识别所述单线程区域内的依赖性; 确定可以基于分析并行执行执行程序代码的单线程区域的部分; 将所述部分分配给两个或更多个并行执行轨道; 并且在分配的执行轨道上并行地执行这些部分。

公开(公告)号：US20140258677A1

公开(公告)日：2014-09-11

申请号：US13997140

申请日：2013-03-05

Applicant: Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Jayaram Bobba ,  Michael R. Greenfield ,  Suresh Srinivas

Inventor： Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Jayaram Bobba ,  Michael R. Greenfield ,  Suresh Srinivas

IPC: G06F9/30

CPC classification number: G06F8/41 ,  G06F8/456

Abstract: Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data (“SIMD”) instructions.

Abstract translation: 本文描述了计算机实现的方法，系统，计算设备和计算机可读介质（暂时性和非暂时性）的实施例，用于分析多个可执行指令的执行，并且基于该分析，提供对 可以通过对多个可执行指令的至少一个子集进行向量化来获得。 在各种实施例中，分析可以包括识别适合于转换成一个或多个单指令多数据（“SIMD”）指令的多个可执行指令的子集。