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    Write ordering for microprocessor depending on cache hit and write buffer content
    9.
    发明授权
    Write ordering for microprocessor depending on cache hit and write buffer content 失效
    根据缓存命中和写缓冲区内容，为微处理器写入顺序

    公开(公告)号：US5379396A

    公开(公告)日：1995-01-03

    申请号：US777765

    申请日：1991-10-11

    申请人： Simcha Gochman ,  Itamar Kazachinsky ,  Michael Kagan

    发明人： Simcha Gochman ,  Itamar Kazachinsky ,  Michael Kagan

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/16

    CPC分类号： G06F12/0804 ,  G06F12/1045

    摘要： An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.

    摘要翻译： 具有缓存存储器的微处理器的改进提供强而弱的写入顺序模式。 微处理器包括用于接收指示外部写入缓冲器是否为空的信号的端子和指示内部写入缓冲器是否为空的内部信号。 如果写入缓冲区不为空，并且在写入周期期间发生命中条件，直到缓冲区为空，微处理器的操作将以强排序模式停止。

    Method and apparatus for reducing clock frequency during low workload periods
    10.
    发明申请
    Method and apparatus for reducing clock frequency during low workload periods 有权

    公开(公告)号：US20060129860A1

    公开(公告)日：2006-06-15

    申请号：US11330647

    申请日：2006-01-12

    申请人： Itamar Kazachinsky ,  Doron Orenstein

    发明人： Itamar Kazachinsky ,  Doron Orenstein

    IPC分类号： G06F1/32

    CPC分类号： G06F1/324 ,  G06F1/3203 ,  Y02D10/126

    摘要： A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal. In one embodiment, the GC masks out selected cycles of the clock generator output to reduce the clock signal frequency. The FSM monitors the operation of the IC to transition from the first state to the second state when selected “low workload” conditions are detected (e.g., long latency cache miss). Similarly, the FSM transitions from the second state to the first state when selected “non-low workload” conditions are detected.