Memory Disambiguation Hardware To Support Software Binary Translation
    2.
    发明申请
    Memory Disambiguation Hardware To Support Software Binary Translation 有权
    内存消歧硬件支持软件二进制翻译

    公开(公告)号:US20130262838A1

    公开(公告)日:2013-10-03

    申请号:US13435165

    申请日:2012-03-30

    IPC分类号: G06F9/30

    摘要: A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.

    摘要翻译: 提供了一种支持软件二进制翻译的内存消歧硬件的方法。 该方法包括展开要在处理器内执行的一组指令,该组指令具有多个存储器操作。 确定存储器操作的原始相对顺序。 然后,在软件中检测和识别可能的重排序问题。 重新排序问题是在第一存储器操作已经在存储器操作的原始顺序之前被重新排序并且相对于第二存储器操作而被重新排序的时候。 解决了重新排序问题,并且传达到处理器的存储器操作的相对顺序。

    Detecting and Filtering Biased Branches in Global Branch History
    3.
    发明申请
    Detecting and Filtering Biased Branches in Global Branch History 审中-公开
    在全球分支机构历史中检测和筛选偏倚分支

    公开(公告)号:US20140156978A1

    公开(公告)日:2014-06-05

    申请号:US13691049

    申请日:2012-11-30

    IPC分类号: G06F9/38

    CPC分类号: G06F9/3848

    摘要: A processor includes an instruction pipeline for executing instructions including a branching instruction, a counter for counting times that the branching instruction is taken, a register for storing a global branch history as a function of a value of the counter, and a branch prediction unit for predicting branching based on the global branch history.

    摘要翻译: 处理器包括用于执行指令的指令流水线,所述指令包括分支指令,用于计数分支指令的计数次数的计数器,用于存储作为计数器的值的函数的全局分支历史的寄存器,以及分支预测单元, 根据全球分支历史预测分支。

    Predictors with Adaptive Prediction Threshold
    5.
    发明申请
    Predictors with Adaptive Prediction Threshold 失效
    具有自适应预测阈值的预测器

    公开(公告)号:US20100306515A1

    公开(公告)日:2010-12-02

    申请号:US12473764

    申请日:2009-05-28

    IPC分类号: G06F9/38

    CPC分类号: G06F9/3848

    摘要: An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine for a PHT entry is obtained. Count values in a set of counters allocated to the entry in the PHT are changed based on the count value of the entry's prediction state counter. The prediction threshold of the prediction state machine for the entry may then be adjusted based on the changed count values in the set of counters, wherein the prediction threshold is adjusted by changing a count value in a prediction threshold counter in the entry, and wherein adjusting the prediction threshold redefines predictions provided by the prediction state machine.

    摘要翻译: 一种自适应预测阈值方案,用于通过观察索引到PHT条目中的分支或分支的全局倾向来动态地调整模式历史表(PHT)中条目的预测阈值。 获得表示PHT条目的预测状态机的预测状态的预测状态计数器的计数值。 分配给PHT中的条目的一组计数器中的计数值根据条目的预测状态计数器的计数值而改变。 然后可以基于该组计数器中的改变的计数值来调整用于该条目的预测状态机的预测阈值,其中通过改变条目中的预测阈值计数器中的计数值来调整预测阈值,并且其中调整 预测阈值重新定义了由预测状态机提供的预测。

    Memory disambiguation hardware to support software binary translation
    7.
    发明授权
    Memory disambiguation hardware to support software binary translation 有权
    内存消歧硬件支持软件二进制翻译

    公开(公告)号:US08826257B2

    公开(公告)日:2014-09-02

    申请号:US13435165

    申请日:2012-03-30

    IPC分类号: G06F9/45

    摘要: A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.

    摘要翻译: 提供了一种支持软件二进制翻译的内存消歧硬件的方法。 该方法包括展开要在处理器内执行的一组指令,该组指令具有多个存储器操作。 确定存储器操作的原始相对顺序。 然后,在软件中检测和识别可能的重排序问题。 重新排序问题是在第一存储器操作已经在存储器操作的原始顺序之前被重新排序并且相对于第二存储器操作而被重新排序的时候。 解决了重新排序问题,并且传达到处理器的存储器操作的相对顺序。

    MEMORY ADDRESS ALIASING DETECTION
    8.
    发明申请
    MEMORY ADDRESS ALIASING DETECTION 有权
    存储器寻址检测

    公开(公告)号:US20140089271A1

    公开(公告)日:2014-03-27

    申请号:US13628634

    申请日:2012-09-27

    IPC分类号: G06F7/00 G06F17/30

    摘要: Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained. A current state of the memory address may be identified. The current state may include whether the memory address is associated with a read or a store instruction, and whether the memory address is associated with a set or a check. A previously accumulated state associated with the memory address may be retrieved from a data structure. The previously accumulated state may include whether the memory address was previously associated with a read or a store instruction, and whether the memory address was previously associated with a set or a check. If a transition from the previously accumulated state to the current state is invalid, a failure condition may be signaled.

    摘要翻译: 有效检测违反数据依赖关系的方法和装置。 可以获得与计算机指令相关联的存储器地址。 可以识别存储器地址的当前状态。 当前状态可以包括存储器地址是否与读取或存储指令相关联,以及存储器地址是否与集合或检查相关联。 可以从数据结构检索与存储器地址相关联的先前累积状态。 先前累积的状态可以包括存储器地址是否先前与读取或存储指令相关联,以及存储器地址是否先前与集合或检查相关联。 如果从先前累积状态到当前状态的转换无效,则可以发信号通知故障状态。