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    NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER
    22.
    发明申请
    NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER 有权
    具有分级层的非易失性磁记忆元件

    公开(公告)号：US20130087870A1

    公开(公告)日：2013-04-11

    申请号：US13476904

    申请日：2012-05-21

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L29/82

    CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

    Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。

    Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion
    23.
    发明授权
    Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion 有权
    低电流切换磁隧道结设计，用于使用畴壁运动的磁存储器

    公开(公告)号：US08164947B2

    公开(公告)日：2012-04-24

    申请号：US12985028

    申请日：2011-01-05

    Applicant: Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

    IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15

    CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L43/08

    Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

    Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

    Magnetic tunnel junction (MTJ) formation with two-step process
    24.
    发明授权
    Magnetic tunnel junction (MTJ) formation with two-step process 有权
    磁隧道结（MTJ）形成两步法

    公开(公告)号：US08148174B1

    公开(公告)日：2012-04-03

    申请号：US13100048

    申请日：2011-05-03

    Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

    Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC: H01L21/00

    CPC classification number: H01L43/12

    Abstract: A method of manufacturing a magnetic memory element includes the steps of performing a first etching an oxide layer is etched, using a first photo-resist, the oxide layer formed on top of a contact layer that is formed on top of a magneto tunnel junction (MTJ), depositing a second photo-resist and second etching to leave a portion of the contact layer used to suitably connect the MTJ to circuits outside of the magnetic memory element.

    Abstract translation: 一种制造磁存储元件的方法包括以下步骤：使用第一光致抗蚀剂进行第一蚀刻，蚀刻氧化层，形成在形成于磁隧道结顶部的接触层顶部上的氧化物层 沉积第二光刻胶和第二蚀刻以留下用于将MTJ适当地连接到磁存储元件外部的电路的接触层的一部分。

    LOW COST MULTI-STATE MAGNETIC MEMORY
    26.
    发明申请
    LOW COST MULTI-STATE MAGNETIC MEMORY 有权
    低成本多状态磁记忆

    公开(公告)号：US20110305078A1

    公开(公告)日：2011-12-15

    申请号：US13216997

    申请日：2011-08-24

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: G11C11/14 ,  H01L29/82

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

    Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

    Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

    Low cost multi-state magnetic memory
    28.
    发明授权
    Low cost multi-state magnetic memory 有权
    低成本多状态磁存储器

    公开(公告)号：US08018011B2

    公开(公告)日：2011-09-13

    申请号：US11860467

    申请日：2007-09-24

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L29/82 ,  G11C11/00

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

    Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

    Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

    Embedded Magnetic Random Access Memory (MRAM)
    29.
    发明申请
    Embedded Magnetic Random Access Memory (MRAM) 有权
    嵌入式磁随机存取存储器（MRAM）

    公开(公告)号：US20100221848A1

    公开(公告)日：2010-09-02

    申请号：US12778725

    申请日：2010-05-12

    Applicant: Parviz KESHTBOD ,  Ebrahim ABEDIFARD

    Inventor： Parviz KESHTBOD ,  Ebrahim ABEDIFARD

    IPC: H01L21/00

    CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

    Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

    Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

    SENSING AND WRITING TO MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    30.
    发明申请
    SENSING AND WRITING TO MAGNETIC RANDOM ACCESS MEMORY (MRAM) 有权
    磁性随机存取存储器（MRAM）的传感和写入

    公开(公告)号：US20090154229A1

    公开(公告)日：2009-06-18

    申请号：US12125866

    申请日：2008-05-22

    Applicant: Parviz KESHTBOD

    Inventor： Parviz KESHTBOD

    IPC: G11C11/14 ,  G11C7/00 ,  G11C11/416

    CPC classification number: G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693

    Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

    Abstract translation: 感测电路包括具有第一和第二节点的读出放大器电路，通过该第一和第二节点检测磁存储元件。 第一电流源耦合到第一节点，第二电流源耦合到第二节点。 参考磁存储元件具有与之相关联的电阻并且耦合到第一节点，参考磁存储元件从第一电流源接收电流。 具有与其相关联的电阻的至少一个存储元件耦合到第二节点并从第二电流源接收电流。 来自第一电流源的电流和来自第二电流源的电流基本上相同。 通过比较至少一个存储元件的电阻与参考磁存储元件的电阻来感测至少一个存储元件的逻辑状态。

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