公开(公告)号：US20130329488A1

公开(公告)日：2013-12-12

申请号：US13491159

申请日：2012-06-07

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1657

Abstract: A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state.

Abstract translation: 通过施加第一参考电流来感测MTJ，首先使用第一参考电流将MTJ编程为第一值，检测第一编程MTJ的电阻，并且如果检测到的电阻高于第一参考电阻，则将MTJ声明为 处于第一个状态。 否则，在确定检测到的电阻是否低于第二参考电阻时，声明MTJ处于第二状态。 在某些情况下，通过MTJ施加第二参考电流，并使用第二参考电流对MTJ进行第二次编程。 检测第二个编程的MTJ的电阻，并且在某些情况下，声明MTJ处于第二状态，在其他情况下，声明MTJ处于第一状态并将MTJ编程到第二状态。

公开(公告)号：US08574928B2

公开(公告)日：2013-11-05

申请号：US13443818

申请日：2012-04-10

Applicant: Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Abstract translation: 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US08477529B2

公开(公告)日：2013-07-02

申请号：US13623054

申请日：2012-09-19

Applicant: Parviz Keshtbod ,  Ebrahim Abedifard

Inventor： Parviz Keshtbod ,  Ebrahim Abedifard

IPC: G11C11/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US08148174B1

公开(公告)日：2012-04-03

申请号：US13100048

申请日：2011-05-03

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L43/12

Abstract: A method of manufacturing a magnetic memory element includes the steps of performing a first etching an oxide layer is etched, using a first photo-resist, the oxide layer formed on top of a contact layer that is formed on top of a magneto tunnel junction (MTJ), depositing a second photo-resist and second etching to leave a portion of the contact layer used to suitably connect the MTJ to circuits outside of the magnetic memory element.

Abstract translation: 一种制造磁存储元件的方法包括以下步骤：使用第一光致抗蚀剂进行第一蚀刻，蚀刻氧化层，形成在形成于磁隧道结顶部的接触层顶部上的氧化物层 沉积第二光刻胶和第二蚀刻以留下用于将MTJ适当地连接到磁存储元件外部的电路的接触层的一部分。

公开(公告)号：US20120282711A1

公开(公告)日：2012-11-08

申请号：US13371380

申请日：2012-02-10

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: H01L21/02

CPC classification number: H01L43/12

Abstract: A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting.

Abstract translation: 一种制造磁存储元件的方法包括以下步骤：在底部电极的顶部形成永久磁性层，在永久磁性层的顶部形成钉扎层，形成包含阻挡层的磁性隧道结（MTJ） 钉扎层，在MTJ的顶部形成顶部电极，在顶部电极的顶部上形成硬掩模，并且使用硬掩模执行一系列蚀刻工艺以将MTJ和顶部电极的宽度减小到基本上 当检测到钉扎层中的预定材料时，这些蚀刻工艺中的一个停止，从而避免金属沉积到蚀刻工艺的阻挡层上，从而防止短路。

公开(公告)号：US08883520B2

公开(公告)日：2014-11-11

申请号：US13530381

申请日：2012-06-22

Applicant: Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

Inventor： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

IPC: H01L21/00

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

Abstract translation: 描述了方法和结构以在柱蚀刻期间减少存储器单元（例如MTJ电池）中的金属沉积材料。 一个实施例在位于晶片上暴露的金属表面的电介质层中的着陆焊盘的顶部上形成金属螺柱。 另一个实施例分别对MTJ和底部电极进行图案化。 底部电极掩模然后覆盖底部电极下面的金属。 另一实施例将柱蚀刻工艺分为两个阶段。 第一阶段蚀刻到较低的磁性层，然后阻挡层的侧壁被电介质材料覆盖，然后将其垂直蚀刻。 蚀刻的第二阶段然后对剩余的层进行图案化。 另一个实施例使用顶部电极上方的硬掩模来蚀刻MTJ柱直到靠近底部电极的端点，沉积电介质，然后垂直蚀刻剩余的底部电极。

公开(公告)号：US08670264B1

公开(公告)日：2014-03-11

申请号：US13585774

申请日：2012-08-14

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/21

CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

Abstract translation: 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。

公开(公告)号：US08644060B2

公开(公告)日：2014-02-04

申请号：US13491159

申请日：2012-06-07

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/1673 ,  G11C11/1657

Abstract: A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state.

Abstract translation: 通过施加第一参考电流来感测MTJ，首先使用第一参考电流将MTJ编程为第一值，检测第一编程MTJ的电阻，并且如果检测到的电阻高于第一参考电阻，则将MTJ声明为 处于第一个状态。 否则，在确定检测到的电阻是否低于第二参考电阻时，声明MTJ处于第二状态。 在某些情况下，通过MTJ施加第二参考电流，并使用第二参考电流对MTJ进行第二次编程。 检测第二个编程的MTJ的电阻，并且在某些情况下，声明MTJ处于第二状态，在其他情况下，声明MTJ处于第一状态并将MTJ编程到第二状态。

公开(公告)号：US20130341801A1

公开(公告)日：2013-12-26

申请号：US13530381

申请日：2012-06-22

Applicant: Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

Inventor： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

公开(公告)号：US20140192590A1

公开(公告)日：2014-07-10

申请号：US14204274

申请日：2014-03-11

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

Abstract translation: 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。