公开(公告)号：US20050047196A1

公开(公告)日：2005-03-03

申请号：US10649200

申请日：2003-08-27

申请人： Azeez Bhavnagarwala ,  Rajiv Joshi ,  Stephen Kosonocky

发明人： Azeez Bhavnagarwala ,  Rajiv Joshi ,  Stephen Kosonocky

IPC分类号： G11C11/418 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C11/412

摘要： Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation. A method is implemented for dynamically adjusting the threshold voltages of the transistors of activated memory cells during an access operation to thereby increase the read current or performance of the accessed memory cells.

摘要翻译： 无负载4T SRAM单元以及用于操作这样的SRAM单元的方法，其可以提供高度集成的半导体存储器件，同时在数据访问操作方面提供相对于数据稳定性和增加的I / O速度的增加的性能。 无负载的4T SRAM单元包括一对存取晶体管和一对下拉晶体管，所有这些都被实现为N沟道晶体管（NFET或NMOSFETS）。 存取晶体管具有比下拉晶体管低的阈值电压，这使得SRAM单元能够在待机期间有效地保持逻辑“1”电位。 与存取晶体管相比，下拉晶体管具有较大的沟道宽度，这使得SRAM单元能够在读取操作期间在给定存储节点处有效地保持逻辑“0”电位。 实现了一种用于在访问操作期间动态地调整激活的存储器单元的晶体管的阈值电压从而增加所访问的存储器单元的读取电流或性能的方法。

公开(公告)号：US20050040881A1

公开(公告)日：2005-02-24

申请号：US10644211

申请日：2003-08-20

申请人： Richard Brown ,  Ching-Te Chuang ,  Peter Cook ,  Koushik Das ,  Rajiv Joshi

发明人： Richard Brown ,  Ching-Te Chuang ,  Peter Cook ,  Koushik Das ,  Rajiv Joshi

IPC分类号： H03K19/00 ,  H03K3/01

CPC分类号： H03K19/0016

摘要： A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETS) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.

摘要翻译： 具有降低的亚阈值泄漏的多阈值集成电路（IC）和减少泄漏的方法。 电路逻辑电路和电源连接（Vdd和Ground）之间的可选供电开关器件（NFET和/或PFETS）具有比正常电路器件更高的阈值。 当供电开关装置打开时，一些装置可能具有降低的阈值。 具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。 或者，可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。 中间电源连接在器件上可能具有去耦电容，器件可以锥形化，以获得最佳堆叠高度和最佳锥度比，以最大限度地减少电路泄漏和电路延迟。

公开(公告)号：US20150057231A1

公开(公告)日：2015-02-26

申请号：US14381807

申请日：2012-02-29

申请人： Alain Prochiantz ,  Kenneth Moya ,  Rajiv Joshi

发明人： Alain Prochiantz ,  Kenneth Moya ,  Rajiv Joshi

IPC分类号： A61K38/17

CPC分类号： A61K38/1709

摘要： The invention relates to the use of an Engrailed protein as a medicament for increasing dopamine synthesis by dopaminergic neurons, in particular in the management of conditions associated with a decrease of dopamine levels without loss of dopaminergic neurons

摘要翻译： 本发明涉及使用Engrailed蛋白作为多巴胺能神经元增加多巴胺合成药物的用途，特别是在与多巴胺水平降低相关的病症的管理中，而不损失多巴胺能神经元

公开(公告)号：US08255359B2

公开(公告)日：2012-08-28

申请号：US12645799

申请日：2009-12-23

申请人： Sean M. Quinlan ,  Daniel J. Mendez ,  Rajiv Joshi ,  Yuri Ardulov

发明人： Sean M. Quinlan ,  Daniel J. Mendez ,  Rajiv Joshi ,  Yuri Ardulov

IPC分类号： G06F17/00 ,  G06F7/00

CPC分类号： H04L67/1095 ,  G06F9/52 ,  G06F17/30578 ,  Y10S707/99955

摘要： Aspects of the advancement provide for information to be synchronized in an asynchronous manner among two or more computing devices.

摘要翻译： 进步的方面提供了在两个或更多个计算设备之间以异步方式同步的信息。

公开(公告)号：US20080019200A1

公开(公告)日：2008-01-24

申请号：US11782282

申请日：2007-07-24

申请人： YUEN CHAN ,  RAJIV JOSHI ,  DONALD PLASS

发明人： YUEN CHAN ,  RAJIV JOSHI ,  DONALD PLASS

IPC分类号： G11C5/06

CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

公开(公告)号：US20070291562A1

公开(公告)日：2007-12-20

申请号：US11838341

申请日：2007-08-14

申请人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

摘要翻译： 用于评估静态存储单元动态稳定性的内部非对称方法和电路为提高存储器阵列的性能提供了超越现有水平/产量的机制。 通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

公开(公告)号：US20070153599A1

公开(公告)日：2007-07-05

申请号：US11685905

申请日：2007-03-14

申请人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.

摘要翻译： 用于评估对静态存储器单元访问时间的泄漏影响的方法提供了一种用于提高存储器阵列的性能超过现有水平/产量的机制。 通过改变与被测试的静态存储器单元连接到同一位线的其它静态存储单元的状态，可以观察到泄漏对单元访问时间的影响。 可以进一步观察泄漏效应，同时改变存储器单元的内部对称性，操作电池并观察不对称操作引起的性能变化。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。

公开(公告)号：US20060256605A1

公开(公告)日：2006-11-16

申请号：US11128675

申请日：2005-05-13

申请人： Rajiv Joshi

发明人： Rajiv Joshi

IPC分类号： G11C17/00

CPC分类号： G11C11/417

摘要： A random access memory includes a logic circuit coupled to a power supply of a column having a memory cell. The logic circuit adjusts the supply voltage for the memory cell in the column in accordance with a control signal. A control circuit is coupled to the logic circuit, which generates the control signal in accordance with an operation type and whether the column is selected, such that the logic circuit selects the supply voltage in accordance with the control signal. The cell may include high mobility devices to improve performance.

摘要翻译： 随机存取存储器包括耦合到具有存储单元的列的电源的逻辑电路。 逻辑电路根据控制信号调整列中的存储单元的电源电压。 控制电路耦合到逻辑电路，其根据操作类型产生控制信号，以及是否选择列，使得逻辑电路根据控制信号选择电源电压。 该小区可以包括高移动性设备以提高性能。

公开(公告)号：US20060250860A1

公开(公告)日：2006-11-09

申请号：US11483117

申请日：2006-07-06

申请人： Rajiv Joshi

发明人： Rajiv Joshi

IPC分类号： G11C7/00

CPC分类号： G11C11/413 ,  G11C8/08

摘要： A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

摘要翻译： 随机存取存储器包括具有存取装置的存储单元。 接入设备根据字线上的信号被接通或断开，以通过接入设备进行存储器操作。 逻辑电路耦合到字线以延迟或栅极字线信号，直到使能信号到达逻辑电路。 访问设备提高了稳定性并消除了早期读取问题。

公开(公告)号：US20060203581A1

公开(公告)日：2006-09-14

申请号：US11077313

申请日：2005-03-10

申请人： Rajiv Joshi ,  Anirudh Devgan

发明人： Rajiv Joshi ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G06F17/5045 ,  G06F2217/10

摘要： An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to 15 each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield. Multiple cell designs can be compared for performance, yield and sensitivity of performance variables to circuit parameters over particular environmental conditions in order to select the best cell design.

摘要翻译： 一种有效的方法和计算机程序，用于建模和改进在过程变化和环境条件之间的记忆性能，为提高存储器阵列的性能提供了超出当前水平/产量的机制。 对于多个存储器性能变量中的每一个执行电路参数子集的统计（蒙特卡罗）分析，然后确定每个性能变量对每个电路参数的灵敏度。 然后根据敏感度调整存储器单元的存储单元设计参数和/或操作条件，从而提高存储器产量和/或性能。 一旦达到性能水平，然后可以使用敏感度来改变性能变量的概率分布，以获得更高的产量。 为了选择最佳的单元设计，可以将多个单元设计与性能变量的性能，产出和灵敏度进行比较，以便在特定的环境条件下对电路参数进行比较。