公开(公告)号：US20050120328A1

公开(公告)日：2005-06-02

申请号：US10987427

申请日：2004-11-12

Applicant: Rolf Seltmann ,  Heiko Wagner ,  Rolf Stephan

Inventor： Rolf Seltmann ,  Heiko Wagner ,  Rolf Stephan

IPC: G03F7/00 ,  G03F7/20 ,  G06F17/50 ,  H01L21/66

CPC classification number: G03F7/70658 ,  G03F7/70558

Abstract: The electrical performance of sub-devices is detected and the corresponding measurement data is used to control a lithography process so as to compensate for any type of process variations during a manufacturing sequence.

Abstract translation: 检测到子器件的电气性能，并且使用相应的测量数据来控制光刻工艺，以补偿制造顺序期间的任何类型的工艺变化。

公开(公告)号：US06881641B2

公开(公告)日：2005-04-19

申请号：US10282980

申请日：2002-10-29

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/331

CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/6659

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract translation: 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

公开(公告)号：US06770552B2

公开(公告)日：2004-08-03

申请号：US10400706

申请日：2003-03-27

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L21336

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659

Abstract: The cross-sectional area of polysilicon lines is increased by selectively epitaxially growing an upper portion of the polysilicon line in the presence of a dielectric layer exposing the upper portion. Thus, a substantially T-shaped line is obtained, allowing a minimum bottom-CD while insuring a sufficient high conductivity.

Abstract translation: 在存在暴露上部的电介质层的情况下，通过选择性地外延生长多晶硅线的上部来增加多晶硅线的横截面面积。 因此，获得基本上T形的线，允许最小的底部CD，同时确保足够的高导电性。

公开(公告)号：US06492210B2

公开(公告)日：2002-12-10

申请号：US09810771

申请日：2001-03-16

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan ,  Michael Raab

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan ,  Michael Raab

IPC: H01L2100

CPC classification number: H01L29/66772 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78621

Abstract: This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Abstract translation: 本发明提供了在基于用于形成器件隔离特征和源极和漏极区域的栅电极和侧壁间隔物屏蔽程序的基础上使用自对准技术在集成电路中形成场效应晶体管的方法。 本发明能够增加半导体器件的积分密度，使场效应晶体管器件中的寄生电容最小化，以及更快的制造工艺。

公开(公告)号：US06423634B1

公开(公告)日：2002-07-23

申请号：US09557697

申请日：2000-04-25

Applicant: Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

IPC: H01L2144

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/66545

Abstract: In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.

Abstract translation: 在一个实施例中，在漏极和源极区域上形成低电阻金属硅化物区域之前，在晶体管器件的栅电极的顶表面上形成保护层。 保护层防止在栅电极上同时形成金属硅化物区域。 此后，在位于栅电极上方的源极/漏极区域和覆盖层之上形成处理层。 接下来，将处理层的表面平坦化以露出覆盖层，并且去除覆盖层。 然后，通过沉积难熔金属层并进行至少一个退火工艺，在栅电极上方形成金属硅化物区域。

公开(公告)号：US08735236B2

公开(公告)日：2014-05-27

申请号：US13339842

申请日：2011-12-29

Applicant: Klaus Hempel ,  Christopher Prindle ,  Rolf Stephan

Inventor： Klaus Hempel ,  Christopher Prindle ,  Rolf Stephan

IPC: H01L21/338

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/518 ,  H01L29/66545

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer.

Abstract translation: 当在更换栅极方法的基础上形成复杂的高k金属栅电极结构时，填充高导电电极金属（例如铝）时的填充条件可以通过去除最终功函数金属例如钛 P沟道晶体管中的氮化物材料，仅保留了明确的底层。

公开(公告)号：US20130168773A1

公开(公告)日：2013-07-04

申请号：US13339842

申请日：2011-12-29

Applicant: Klaus Hempel ,  Christopher Prindle ,  Rolf Stephan

Inventor： Klaus Hempel ,  Christopher Prindle ,  Rolf Stephan

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/66

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/518 ,  H01L29/66545

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer.

Abstract translation: 当在更换栅极方法的基础上形成复杂的高k金属栅电极结构时，填充高导电电极金属（例如铝）时的填充条件可以通过去除最终功函数金属例如钛 P沟道晶体管中的氮化物材料，仅保留了明确的底层。

公开(公告)号：US20110045665A1

公开(公告)日：2011-02-24

申请号：US12916681

申请日：2010-11-01

Applicant: Martin Trentzsch ,  Thorsten Kammler ,  Rolf Stephan

Inventor： Martin Trentzsch ,  Thorsten Kammler ,  Rolf Stephan

IPC: H01L21/3205

CPC classification number: H01L21/28158 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.

Abstract translation: 通过基于氢环境进行热处理，暴露的含硅表面部分可以在形成栅极电介质材料之前重组。 因此，可以提高栅极电介质的界面质量和材料特性，从而降低高标度P沟道晶体管中的负偏压温度不稳定性的影响。

公开(公告)号：US20090170339A1

公开(公告)日：2009-07-02

申请号：US12125490

申请日：2008-05-22

Applicant: Martin Trentzsch ,  Thorsten Kammler ,  Rolf Stephan

Inventor： Martin Trentzsch ,  Thorsten Kammler ,  Rolf Stephan

IPC: H01L21/283

CPC classification number: H01L21/28158 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.

Abstract translation: 通过基于氢环境进行热处理，暴露的含硅表面部分可以在形成栅极电介质材料之前重组。 因此，可以提高栅极电介质的界面质量和材料特性，从而降低高标度P沟道晶体管中的负偏压温度不稳定性的影响。

公开(公告)号：US20080081471A1

公开(公告)日：2008-04-03

申请号：US11736939

申请日：2007-04-18

Applicant: Patrick Press ,  Karla Romero ,  Martin Trentzsch ,  Karsten Wieczorek ,  Thomas Feudel ,  Markus Lenski ,  Rolf Stephan

Inventor： Patrick Press ,  Karla Romero ,  Martin Trentzsch ,  Karsten Wieczorek ,  Thomas Feudel ,  Markus Lenski ,  Rolf Stephan

IPC: H01L21/44

CPC classification number: H01L21/268 ,  H01L21/823807 ,  H01L27/11 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.

Abstract translation: 通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。 此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。